Reconfigurable Computing Systems for Robotics using a Component-Oriented Approach

Robotic platforms are becoming more complex due to the wide range of modern applications, including multiple heterogeneous sensors and actuators. In order to comply with real-time and power-consumption constraints, these systems need to process a large amount of heterogeneous data from multiple sensors and take action (via actuators), which represents a problem as the resources of these systems have limitations in memory storage, bandwidth, and computational power. Field Programmable Gate Arrays (FPGAs) are programmable logic devices that offer high-speed parallel processing. FPGAs are particularly well-suited for applications that require real-time processing, high bandwidth, and low latency. One of the fundamental advantages of FPGAs is their flexibility in designing hardware tailored to specific needs, making them adaptable to a wide range of applications. They can be programmed to pre-process data close to sensors, which reduces the amount of data that needs to be transferred to other computing resources, improving overall system efficiency. Additionally, the reprogrammability of FPGAs enables them to be repurposed for different applications, providing a cost-effective solution that needs to adapt quickly to changing demands. FPGAs' performance per watt is close to that of Application-Specific Integrated Circuits (ASICs), with the added advantage of being reprogrammable. Despite all the advantages of FPGAs (e.g., energy efficiency, computing capabilities), the robotics community has not fully included them so far as part of their systems for several reasons. First, designing FPGA-based solutions requires hardware knowledge and longer development times as their programmability is more challenging than Central Processing Units (CPUs) or Graphics Processing Units (GPUs). Second, porting a robotics application (or parts of it) from software to an accelerator requires adequate interfaces between software and FPGAs. Third, the robotics workflow is already complex on its own, combining several fields such as mechanics, electronics, and software. There have been partial contributions in the state-of-the-art for FPGAs as part of robotics systems. However, a study of FPGAs as a whole for robotics systems is missing in the literature, which is the primary goal of this dissertation. Three main objectives have been established to accomplish this. (1) Define all components required for an FPGAs-based system for robotics applications as a whole. (2) Establish how all the defined components are related. (3) With the help of Model-Driven Engineering (MDE) techniques, generate these components, deploy them, and integrate them into existing solutions. The component-oriented approach proposed in this dissertation provides a proper solution for designing and implementing FPGA-based designs for robotics applications. The modular architecture, the tool 'FPGA Interfaces for Robotics Middlewares' (FIRM), and the toolchain 'FPGA Architectures for Robotics' (FAR) provide a set of tools and a comprehensive design process that enables the development of complex FPGA-based designs more straightforwardly and efficiently. The component-oriented approach contributed to the state-of-the-art in FPGA-based designs significantly for robotics applications and helps to promote their wider adoption and use by specialists with little FPGA knowledge

Integrated Architecture for Configuration and Service Management in MANET Environments

Esta tesis nos ha permitido trasladar algunos conceptos teóricos de la computación ubicua a escenarios reales, identificando las necesidades específicas de diferentes tipos de aplicaciones. Con el fin de alcanzar este objetivo, proponemos dos prototipos que proporcionan servicios sensibles al contexto en diferentes entornos, tales como conferencias o salas de recuperación en hospitales. Estos prototipos experimentales explotan la tecnología Bluetooth para ofrecer información basada en las preferencias del usuario. En ambos casos, hemos llevado a cabo algunos experimentos con el fin de evaluar el comportamiento de los sistemas y su rendimento. También abordamos en esta tesis el problema de la autoconfiguración de redes MANET basadas en el estándar 802.11 a través de dos soluciones novedosas. La primera es una solución centralizada que se basa en la tecnología Bluetooth, mientras la segunda es una solución distribuida que no necesita recurrir a ninguna tecnología adicional, ya que se basa en el uso del parámetro SSID. Ambos métodos se han diseñado para permitir que usuarios no expertos puedan unirse a una red MANET de forma transparente, proporcionando una configuración automática, rápida, y fiable de los terminales. Los resultados experimentales en implementaciones reales nos han permitido evaluar el rendimiento de las soluciones propuestas y demostrar que las estaciones cercanas se pueden configurar en pocos segundos. Además, hemos comparado ambas soluciones entre sí para poner de manifiesto las diferentes ventajas y desventajas en cuanto a rendimento. La principal contribución de esta tesis es EasyMANET, una plataforma ampliable y configurable cuyo objetivo es automatizar lo máximo posible las tareas que afectan a la configuración y puesta en marcha de redes MANET, de modo que su uso sea más simple y accesible.Cano Reyes, J. (2012). Integrated Architecture for Configuration and Service Management in MANET Environments [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/14675Palanci

Demystifying Internet of Things Security

Break down the misconceptions of the Internet of Things by examining the different security building blocks available in Intel Architecture (IA) based IoT platforms. This open access book reviews the threat pyramid, secure boot, chain of trust, and the SW stack leading up to defense-in-depth. The IoT presents unique challenges in implementing security and Intel has both CPU and Isolated Security Engine capabilities to simplify it. This book explores the challenges to secure these devices to make them immune to different threats originating from within and outside the network. The requirements and robustness rules to protect the assets vary greatly and there is no single blanket solution approach to implement security. Demystifying Internet of Things Security provides clarity to industry professionals and provides and overview of different security solutions What You'll Learn Secure devices, immunizing them against different threats originating from inside and outside the network Gather an overview of the different security building blocks available in Intel Architecture (IA) based IoT platforms Understand the threat pyramid, secure boot, chain of trust, and the software stack leading up to defense-in-depth Who This Book Is For Strategists, developers, architects, and managers in the embedded and Internet of Things (IoT) space trying to understand and implement the security in the IoT devices/platforms

Secure Large Scale Penetration of Electric Vehicles in the Power Grid

As part of the approaches used to meet climate goals set by international environmental agreements, policies are being applied worldwide for promoting the uptake of Electric Vehicles (EV)s. The resulting increase in EV sales and the accompanying expansion in the EV charging infrastructure carry along many challenges, mostly infrastructure-related. A pressing need arises to strengthen the power grid to handle and better manage the electricity demand by this mobile and geo-distributed load. Because the levels of penetration of EVs in the power grid have recently started increasing with the increase in EV sales, the real-time management of en-route EVs, before they connect to the grid, is quite recent and not many research works can be found in the literature covering this topic comprehensively. In this dissertation, advances and novel ideas are developed and presented, seizing the opportunities lying in this mobile load and addressing various challenges that arise in the application of public charging for EVs. A Bilateral Decision Support System (BDSS) is developed here for the management of en-route EVs. The BDSS is a middleware-based MAS that achieves a win-win situation for the EVs and the power grid. In this framework, the two are complementary in a way that the desired benefit of one cannot be achieved without attaining that of the other. A Fuzzy Logic based on-board module is developed for supporting the decision of the EV as to which charging station to charge at. GPU computing is used in the higher-end agents to handle the big amount of data resulting in such a large scale system with mobile and geo-distributed nodes. Cyber security risks that threaten the BDSS are assessed and measures are applied to revoke possible attacks. Furthermore, the Collective Distribution of Mobile Loads (CDML), a service with ancillary potential to the power system, is developed. It comprises a system-level optimization. In this service, the EVs requesting a public charging session are collectively redistributed onto charging stations with the objective of achieving the optimal and secure operation of the power system by reducing active power losses in normal conditions and mitigating line congestions in contingency conditions. The CDML uses the BDSS as an industrially viable tool to achieve the outcomes of the optimization in real time. By participating in this service, the EV is considered as an interacting node in the system-wide communication platform, providing both enhanced self-convenience in terms of access to public chargers, and contribution to the collective effort of providing benefit to the power system under the large scale uptake of EVs. On the EV charger level, several advantages have been reported favoring wireless charging of EVs over wired charging. Given that, new techniques are presented that facilitate the optimization of the magnetic link of wireless EV chargers while considering international EMC standards. The original techniques and developments presented in this dissertation were experimentally verified at the Energy Systems Research Laboratory at FIU

5G-PPP Technology Board:Delivery of 5G Services Indoors - the wireless wire challenge and solutions

The 5G Public Private Partnership (5G PPP) has focused its research and innovation activities mainly on outdoor use cases and supporting the user and its applications while on the move. However, many use cases inherently apply in indoor environments whereas their requirements are not always properly reflected by the requirements eminent for outdoor applications. The best example for indoor applications can be found is the Industry 4.0 vertical, in which most described use cases are occurring in a manufacturing hall. Other environments exhibit similar characteristics such as commercial spaces in offices, shopping malls and commercial buildings. We can find further similar environments in the media & entertainment sector, culture sector with museums and the transportation sector with metro tunnels. Finally in the residential space we can observe a strong trend for wireless connectivity of appliances and devices in the home. Some of these spaces are exhibiting very high requirements among others in terms of device density, high-accuracy localisation, reliability, latency, time sensitivity, coverage and service continuity. The delivery of 5G services to these spaces has to consider the specificities of the indoor environments, in which the radio propagation characteristics are different and in the case of deep indoor scenarios, external radio signals cannot penetrate building construction materials. Furthermore, these spaces are usually “polluted” by existing wireless technologies, causing a multitude of interreference issues with 5G radio technologies. Nevertheless, there exist cases in which the co-existence of 5G new radio and other radio technologies may be sensible, such as for offloading local traffic. In any case the deployment of networks indoors is advised to consider and be planned along existing infrastructure, like powerlines and available shafts for other utilities. Finally indoor environments expose administrative cross-domain issues, and in some cases so called non-public networks, foreseen by 3GPP, could be an attractive deployment model for the owner/tenant of a private space and for the mobile network operators serving the area. Technology-wise there exist a number of solutions for indoor RAN deployment, ranging from small cell architectures, optical wireless/visual light communication, and THz communication utilising reconfigurable intelligent surfaces. For service delivery the concept of multi-access edge computing is well tailored to host virtual network functions needed in the indoor environment, including but not limited to functions supporting localisation, security, load balancing, video optimisation and multi-source streaming. Measurements of key performance indicators in indoor environments indicate that with proper planning and consideration of the environment characteristics, available solutions can deliver on the expectations. Measurements have been conducted regarding throughput and reliability in the mmWave and optical wireless communication cases, electric and magnetic field measurements, round trip latency measurements, as well as high-accuracy positioning in laboratory environment. Overall, the results so far are encouraging and indicate that 5G and beyond networks must advance further in order to meet the demands of future emerging intelligent automation systems in the next 10 years. Highly advanced industrial environments present challenges for 5G specifications, spanning congestion, interference, security and safety concerns, high power consumption, restricted propagation and poor location accuracy within the radio and core backbone communication networks for the massive IoT use cases, especially inside buildings. 6G and beyond 5G deployments for industrial networks will be increasingly denser, heterogeneous and dynamic, posing stricter performance requirements on the network. The large volume of data generated by future connected devices will put a strain on networks. It is therefore fundamental to discriminate the value of information to maximize the utility for the end users with limited network resources

Energy-Aware Mobile Learning:Opportunities and Challenges

As mobile devices are becoming more powerful and affordable they are increasingly used for mobile learning activities. By enabling learners' access to educational content anywhere and anytime, mobile learning has both the potential to provide online learners with new opportunities, and to reach less privileged categories of learners that lack access to traditional e-learning services. Among the many challenges with mobile learning, the battery-powered nature of mobile devices and in particular their limited battery life, stands out as one issue that can significantly limit learners' access to educational content while on the move. Adaptation and personalisation solutions have widely been considered for overcoming the differences between learners and between the characteristics of their mobile devices. However, while various energy saving solutions have been proposed in order to provide mobile users with extended device usage time, the areas of adaptive mobile learning and energy conservation in wireless communications failed to meet under the same umbrella. This paper bridges the two areas by presenting an overview of adaptive mobile learning systems as well as how these can be extended to make them energy-aware. Furthermore, the paper surveys various approaches for energy measurement, modelling and adaptation, three major aspects that have to be considered in order to deploy energy-aware mobile learning systems. Discussions on the applicability and limitations of these approaches for mobile learning are also provided

Reconfigurable Antenna Systems: Platform implementation and low-power matters

Antennas are a necessary and often critical component of all wireless systems, of which they share the ever-increasing complexity and the challenges of present and emerging trends. 5G, massive low-orbit satellite architectures (e.g. OneWeb), industry 4.0, Internet of Things (IoT), satcom on-the-move, Advanced Driver Assistance Systems (ADAS) and Autonomous Vehicles, all call for highly flexible systems, and antenna reconfigurability is an enabling part of these advances. The terminal segment is particularly crucial in this sense, encompassing both very compact antennas or low-profile antennas, all with various adaptability/reconfigurability requirements. This thesis work has dealt with hardware implementation issues of Radio Frequency (RF) antenna reconfigurability, and in particular with low-power General Purpose Platforms (GPP); the work has encompassed Software Defined Radio (SDR) implementation, as well as embedded low-power platforms (in particular on STM32 Nucleo family of micro-controller). The hardware-software platform work has been complemented with design and fabrication of reconfigurable antennas in standard technology, and the resulting systems tested. The selected antenna technology was antenna array with continuously steerable beam, controlled by voltage-driven phase shifting circuits. Applications included notably Wireless Sensor Network (WSN) deployed in the Italian scientific mission in Antarctica, in a traffic-monitoring case study (EU H2020 project), and into an innovative Global Navigation Satellite Systems (GNSS) antenna concept (patent application submitted). The SDR implementation focused on a low-cost and low-power Software-defined radio open-source platform with IEEE 802.11 a/g/p wireless communication capability. In a second embodiment, the flexibility of the SDR paradigm has been traded off to avoid the power consumption associated to the relevant operating system. Application field of reconfigurable antenna is, however, not limited to a better management of the energy consumption. The analysis has also been extended to satellites positioning application. A novel beamforming method has presented demonstrating improvements in the quality of signals received from satellites. Regarding those who deal with positioning algorithms, this advancement help improving precision on the estimated position

Embedded electronic systems driven by run-time reconfigurable hardware

Abstract This doctoral thesis addresses the design of embedded electronic systems based on run-time reconfigurable hardware technology –available through SRAM-based FPGA/SoC devices– aimed at contributing to enhance the life quality of the human beings. This work does research on the conception of the system architecture and the reconfiguration engine that provides to the FPGA the capability of dynamic partial reconfiguration in order to synthesize, by means of hardware/software co-design, a given application partitioned in processing tasks which are multiplexed in time and space, optimizing thus its physical implementation –silicon area, processing time, complexity, flexibility, functional density, cost and power consumption– in comparison with other alternatives based on static hardware (MCU, DSP, GPU, ASSP, ASIC, etc.). The design flow of such technology is evaluated through the prototyping of several engineering applications (control systems, mathematical coprocessors, complex image processors, etc.), showing a high enough level of maturity for its exploitation in the industry.Resumen Esta tesis doctoral abarca el diseño de sistemas electrónicos embebidos basados en tecnología hardware dinámicamente reconfigurable –disponible a través de dispositivos lógicos programables SRAM FPGA/SoC– que contribuyan a la mejora de la calidad de vida de la sociedad. Se investiga la arquitectura del sistema y del motor de reconfiguración que proporcione a la FPGA la capacidad de reconfiguración dinámica parcial de sus recursos programables, con objeto de sintetizar, mediante codiseño hardware/software, una determinada aplicación particionada en tareas multiplexadas en tiempo y en espacio, optimizando así su implementación física –área de silicio, tiempo de procesado, complejidad, flexibilidad, densidad funcional, coste y potencia disipada– comparada con otras alternativas basadas en hardware estático (MCU, DSP, GPU, ASSP, ASIC, etc.). Se evalúa el flujo de diseño de dicha tecnología a través del prototipado de varias aplicaciones de ingeniería (sistemas de control, coprocesadores aritméticos, procesadores de imagen, etc.), evidenciando un nivel de madurez viable ya para su explotación en la industria.Resum Aquesta tesi doctoral està orientada al disseny de sistemes electrònics empotrats basats en tecnologia hardware dinàmicament reconfigurable –disponible mitjançant dispositius lògics programables SRAM FPGA/SoC– que contribueixin a la millora de la qualitat de vida de la societat. S’investiga l’arquitectura del sistema i del motor de reconfiguració que proporcioni a la FPGA la capacitat de reconfiguració dinàmica parcial dels seus recursos programables, amb l’objectiu de sintetitzar, mitjançant codisseny hardware/software, una determinada aplicació particionada en tasques multiplexades en temps i en espai, optimizant així la seva implementació física –àrea de silici, temps de processat, complexitat, flexibilitat, densitat funcional, cost i potència dissipada– comparada amb altres alternatives basades en hardware estàtic (MCU, DSP, GPU, ASSP, ASIC, etc.). S’evalúa el fluxe de disseny d’aquesta tecnologia a través del prototipat de varies aplicacions d’enginyeria (sistemes de control, coprocessadors aritmètics, processadors d’imatge, etc.), demostrant un nivell de maduresa viable ja per a la seva explotació a la indústria

Architecting a One-to-many Traffic-Aware and Secure Millimeter-Wave Wireless Network-in-Package Interconnect for Multichip Systems

With the aggressive scaling of device geometries, the yield of complex Multi Core Single Chip(MCSC) systems with many cores will decrease due to the higher probability of manufacturing defects especially, in dies with a large area. Disintegration of large System-on-Chips(SoCs) into smaller chips called chiplets has shown to improve the yield and cost of complex systems. Therefore, platform-based computing modules such as embedded systems and micro-servers have already adopted Multi Core Multi Chip (MCMC) architectures overMCSC architectures. Due to the scaling of memory intensive parallel applications in such systems, data is more likely to be shared among various cores residing in different chips resulting in a significant increase in chip-to-chip traffic, especially one-to-many traffic. This one-to-many traffic is originated mainly to maintain cache-coherence between many cores residing in multiple chips. Besides, one-to-many traffics are also exploited by many parallel programming models, system-level synchronization mechanisms, and control signals. How-ever, state-of-the-art Network-on-Chip (NoC)-based wired interconnection architectures do not provide enough support as they handle such one-to-many traffic as multiple unicast trafficusing a multi-hop MCMC communication fabric. As a result, even a small portion of such one-to-many traffic can significantly reduce system performance as traditional NoC-basedinterconnect cannot mask the high latency and energy consumption caused by chip-to-chipwired I/Os. Moreover, with the increase in memory intensive applications and scaling of MCMC systems, traditional NoC-based wired interconnects fail to provide a scalable inter-connection solution required to support the increased cache-coherence and synchronization generated one-to-many traffic in future MCMC-based High-Performance Computing (HPC) nodes. Therefore, these computation and memory intensive MCMC systems need an energy-efficient, low latency, and scalable one-to-many (broadcast/multicast) traffic-aware interconnection infrastructure to ensure high-performance. Research in recent years has shown that Wireless Network-in-Package (WiNiP) architectures with CMOS compatible Millimeter-Wave (mm-wave) transceivers can provide a scalable, low latency, and energy-efficient interconnect solution for on and off-chip communication. In this dissertation, a one-to-many traffic-aware WiNiP interconnection architecture with a starvation-free hybrid Medium Access Control (MAC), an asymmetric topology, and a novel flow control has been proposed. The different components of the proposed architecture are individually one-to-many traffic-aware and as a system, they collaborate with each other to provide required support for one-to-many traffic communication in a MCMC environment. It has been shown that such interconnection architecture can reduce energy consumption and average packet latency by 46.96% and 47.08% respectively for MCMC systems. Despite providing performance enhancements, wireless channel, being an unguided medium, is vulnerable to various security attacks such as jamming induced Denial-of-Service (DoS), eavesdropping, and spoofing. Further, to minimize the time-to-market and design costs, modern SoCs often use Third Party IPs (3PIPs) from untrusted organizations. An adversary either at the foundry or at the 3PIP design house can introduce a malicious circuitry, to jeopardize an SoC. Such malicious circuitry is known as a Hardware Trojan (HT). An HTplanted in the WiNiP from a vulnerable design or manufacturing process can compromise a Wireless Interface (WI) to enable illegitimate transmission through the infected WI resulting in a potential DoS attack for other WIs in the MCMC system. Moreover, HTs can be used for various other malicious purposes, including battery exhaustion, functionality subversion, and information leakage. This information when leaked to a malicious external attackercan reveals important information regarding the application suites running on the system, thereby compromising the user profile. To address persistent jamming-based DoS attack in WiNiP, in this dissertation, a secure WiNiP interconnection architecture for MCMC systems has been proposed that re-uses the one-to-many traffic-aware MAC and existing Design for Testability (DFT) hardware along with Machine Learning (ML) approach. Furthermore, a novel Simulated Annealing (SA)-based routing obfuscation mechanism was also proposed toprotect against an HT-assisted novel traffic analysis attack. Simulation results show that,the ML classifiers can achieve an accuracy of 99.87% for DoS attack detection while SA-basedrouting obfuscation could reduce application detection accuracy to only 15% for HT-assistedtraffic analysis attack and hence, secure the WiNiP fabric from age-old and emerging attacks