662 research outputs found
A Sound and Complete Axiomatization of Majority-n Logic
Manipulating logic functions via majority operators recently drew the
attention of researchers in computer science. For example, circuit optimization
based on majority operators enables superior results as compared to traditional
logic systems. Also, the Boolean satisfiability problem finds new solving
approaches when described in terms of majority decisions. To support computer
logic applications based on majority a sound and complete set of axioms is
required. Most of the recent advances in majority logic deal only with ternary
majority (MAJ- 3) operators because the axiomatization with solely MAJ-3 and
complementation operators is well understood. However, it is of interest
extending such axiomatization to n-ary majority operators (MAJ-n) from both the
theoretical and practical perspective. In this work, we address this issue by
introducing a sound and complete axiomatization of MAJ-n logic. Our
axiomatization naturally includes existing majority logic systems. Based on
this general set of axioms, computer applications can now fully exploit the
expressive power of majority logic.Comment: Accepted by the IEEE Transactions on Computer
New Symmetric and Planar Designs of Reversible Full-Adders/Subtractors in Quantum-Dot Cellular Automata
Quantum-dot Cellular Automata (QCA) is one of the emerging nanotechnologies,
promising alternative to CMOS technology due to faster speed, smaller size,
lower power consumption, higher scale integration and higher switching
frequency. Also, power dissipation is the main limitation of all the nano
electronics design techniques including the QCA. Researchers have proposed the
various mechanisms to limit this problem. Among them, reversible computing is
considered as the reliable solution to lower the power dissipation. On the
other hand, adders are fundamental circuits for most digital systems. In this
paper, Innovation is divided to three sections. In the first section, a method
for converting irreversible functions to a reversible one is presented. This
method has advantages such as: converting of irreversible functions to
reversible one directly and as optimal. So, in this method, sub-optimal methods
of using of conventional reversible blocks such as Toffoli and Fredkin are not
used, having of minimum number of garbage outputs and so on. Then, Using the
method, two new symmetric and planar designs of reversible full-adders are
presented. In the second section, a new symmetric, planar and fault tolerant
five-input majority gate is proposed. Based on the designed gate, a reversible
full-adder are presented. Also, for this gate, a fault-tolerant analysis is
proposed. And in the third section, three new 8-bit reversible
full-adder/subtractors are designed based on full-adders/subtractors proposed
in the second section. The results are indicative of the outperformance of the
proposed designs in comparison to the best available ones in terms of area,
complexity, delay, reversible/irreversible layout, and also in logic level in
terms of garbage outputs, control inputs, number of majority and NOT gates
New Symmetric and Planar Designs of Reversible Full-Adders/Subtractors in Quantum-Dot Cellular Automata
Quantum-dot Cellular Automata (QCA) is one of the emerging nanotechnologies,
promising alternative to CMOS technology due to faster speed, smaller size,
lower power consumption, higher scale integration and higher switching
frequency. Also, power dissipation is the main limitation of all the nano
electronics design techniques including the QCA. Researchers have proposed the
various mechanisms to limit this problem. Among them, reversible computing is
considered as the reliable solution to lower the power dissipation. On the
other hand, adders are fundamental circuits for most digital systems. In this
paper, Innovation is divided to three sections. In the first section, a method
for converting irreversible functions to a reversible one is presented. This
method has advantages such as: converting of irreversible functions to
reversible one directly and as optimal. So, in this method, sub-optimal methods
of using of conventional reversible blocks such as Toffoli and Fredkin are not
used, having of minimum number of garbage outputs and so on. Then, Using the
method, two new symmetric and planar designs of reversible full-adders are
presented. In the second section, a new symmetric, planar and fault tolerant
five-input majority gate is proposed. Based on the designed gate, a reversible
full-adder are presented. Also, for this gate, a fault-tolerant analysis is
proposed. And in the third section, three new 8-bit reversible
full-adder/subtractors are designed based on full-adders/subtractors proposed
in the second section. The results are indicative of the outperformance of the
proposed designs in comparison to the best available ones in terms of area,
complexity, delay, reversible/irreversible layout, and also in logic level in
terms of garbage outputs, control inputs, number of majority and NOT gates
Cellular Automata
Modelling and simulation are disciplines of major importance for science and engineering. There is no science without models, and simulation has nowadays become a very useful tool, sometimes unavoidable, for development of both science and engineering. The main attractive feature of cellular automata is that, in spite of their conceptual simplicity which allows an easiness of implementation for computer simulation, as a detailed and complete mathematical analysis in principle, they are able to exhibit a wide variety of amazingly complex behaviour. This feature of cellular automata has attracted the researchers' attention from a wide variety of divergent fields of the exact disciplines of science and engineering, but also of the social sciences, and sometimes beyond. The collective complex behaviour of numerous systems, which emerge from the interaction of a multitude of simple individuals, is being conveniently modelled and simulated with cellular automata for very different purposes. In this book, a number of innovative applications of cellular automata models in the fields of Quantum Computing, Materials Science, Cryptography and Coding, and Robotics and Image Processing are presented
An optimized 128-bit cellular automata-based hash function for authentication of data at rest and in transit
The cryptographic hash functions are the most fundamental cryptographic concept. These functions are used as basic building blocks for digital signatures and message authentication. Boolean functions are the core of hash functions. These functions are expected to provide pseudo-randomness as well as input sensitivity. Cellular automata are a form of Boolean function that exhibits strong cryptography properties as well as chaotic behavior. This paper proposes a hash function, designed on the principle of cellular automata. The proposed algorithm is secure and meets the requirements for a successful hashing scheme. The hash function has strong statistical and cryptographic characteristics, according to the findings of the avalanche test and the National Institute of Standards and Technology (NIST) Statistical Test Suite. The modularity of different operations of this algorithm makes it suitable for a high-capacity processing environment to produce efficient performance
Phase Transitions of Cellular Automata
We explore some aspects of phase transitions in cellular automata. We start
recalling the standard formulation of statistical mechanics of discrete systems
(Ising model), illustrating the Monte Carlo approach as Markov chains and
stochastic processes. We then formulate the cellular automaton problem using
simple models, and illustrate different types of possible phase transitions:
density phase transitions of first and second order, damage spreading, dilution
of deterministic rules, asynchronism-induced transitions, synchronization
phenomena, chaotic phase transitions and the influence of the topology. We
illustrate the improved mean-field techniques and the phenomenological
renormalization group approach.Comment: 13 pages, 14 figure
On The Design Of Low-Complexity High-Speed Arithmetic Circuits In Quantum-Dot Cellular Automata Nanotechnology
For the last four decades, the implementation of very large-scale integrated systems has largely based on complementary metal-oxide semiconductor (CMOS) technology. However, this technology has reached its physical limitations. Emerging nanoscale technologies such as quantum-dot cellular automata (QCA), single electron tunneling (SET), and tunneling phase logic (TPL) are major candidate for possible replacements of CMOS. These nanotechnologies use majority and/or minority logic and inverters as circuit primitives. In this dissertation, a comprehensive methodology for majority/minority logic networks synthesis is developed. This method is capable of processing any arbitrary multi-output Boolean function to nd its equivalent optimal majority logic network targeting to optimize either the number of gates or levels. The proposed method results in different primary equivalent majority expression networks. However, the most optimized network will be generated as a nal solution. The obtained results for 15 MCNC benchmark circuits show that when the number of majority gates is the rst optimization priority, there is an average reduction of 45.3% in the number of gates and 15.1% in the number of levels. They also show that when the rst priority is the number of levels, an average reduction of 23.5% in the number of levels and 43.1% in the number of gates is possible, compared to the majority AND/OR mapping method. These results are better compared to those obtained from the best existing methods.
In this dissertation, our approach is to exploit QCA technology because of its capability to implement high-density, very high-speed switching and tremendously lowpower integrated systems and is more amenable to digital circuits design. In particular, we have developed algorithms for the QCA designs of various single- and multi-operation arithmetic arrays. Even though, majority/minority logic are the basic units in promising nanotechnologies, an XOR function can be constructed in QCA as a single device. The basic cells of the proposed arrays are developed based on the fundamental logic devices in QCA and a single-layer structure of the three-input XOR function. This process leads to QCA arithmetic circuits with better results in view of dierent aspects such as cell count, area, and latency, compared to their best counterparts. The proposed arrays can be formed in a pipeline manner to perform the arithmetic operations for any number of bits which could be quite valuable while considering the future design of large-scale QCA circuits
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