Multiform Time in UML for Real-time Embedded Applications

The original publication is available at ieee.org (http://dx.doi.org/10.1109/RTCSA.2007.51)International audienceEach domain has its own interpretation of time. We propose to extend UML, which is more and more used in the domain of real-time embedded applications, with a concept of time inherited from reactive system modeling : multiform time. After a brief review of some UML profiles, we present our extensions and we illustrate on an example from the automotive industry how to represent and to constraint behaviors depending on multiform time. We advocate that this model of time offers wider possibilities than restricting models only to the physical time

A multiform time approach to real-time system modeling: Application to an automotive system

The original publication is available at ieee.org ({http://dx.doi.org/10.1109/SIES.2007.4297340)International audienceIn the context of an effort to answer the OMG RFP for Modeling and Analysis of Real-Time Embedded systems (MARTE), we are defining extensions to the simple time model of UML2. After a brief review of some time-related UML profiles, we focus on the specificity of our approach: the ability to take account of multiform time-a concept inherited from reactive system modeling. Using an example from the automotive industry, we illustrate the use of our profile to represent, to constraint and to analyze behaviors depending on multiform time

Modeling Time(s)

The original publication is available at www.springerlink.com (http://dx.doi.org/10.1007/978-3-540-75209-7_38)International audienceTime and timing features are an important aspect of modern electronic systems, often of embedded nature. We argue here that in early design phases, time is often of logical (rather than physical) nature, even possibly multiform. The compilation/synthesis of heterogeneous applications onto architecture platforms then largely amounts to adjusting the former logical time(s) demands onto the latter physical time abilities. Many distributed scheduling techniques pertain to this approach of “time refinement”. We provide extensive Time and Allocation metamodels that open the possibility to cast this approach in a Model-Driven Engineering light. We give a UML representation of these concepts through two subprofiles, parts of the foundations of the forthcoming OMG UML Profile for Modeling and Analysis of Real-Time and Embedded systems (MARTE). Time modeling also allows for a precise description of time-related entities and their associated timed properties

Transformation de modèles UML vers des programmes Fiacre

Aujourd'hui, le domaine de la modélisation et de la validation formelle de logiciels est un enjeu majeur du génie logiciel. Plus spécifiquement, les architectures logicielles des systèmes embarqués doivent être conçues pour assurer des fonctions critiques soumises à des contraintes très fortes en termes de fiabilité et de performances temps réel. Malgré les progrès techniques, la grande taille de ces systèmes facilite l'introduction d'une plus grande gamme d'erreurs. Alors, les méthodes formelles ont contribué les solutions rigoureuses et puissantes à produire des systèmes non défaillants. Dans ce domaine, les techniques de model-checking ont été fortement popularisées grâce à leur faculté d'exécuter automatiquement des preuves de propriétés sur des modèles logiciels. Alors, il faut pouvoir gérer à partir des modèles UML des codes formels pour différents outils model-checkers selon le type d'analyse que l'on veut mener. Dans ce travail, le langage pivot Fiacre est choisi comme le langage formel intermédiaire de transformation de modèles UML. Ce langage est exploitable par des outils model-checkers OBP Explorer et TINA. On a défini des règles de transformation qui permet de transformer le modèle structurel et fonctionnel UML vers programmes Fiacre. Les diagrammes de classes sont traduits pour construire la structure du système et les diagrammes d'états sont traduits pour construire la dynamique du système. Les diagrammes d'objets sont traduits pour construire la configuration initiale du système. Une classe active UML et sa machine d'état sont traduites par un processus Fiacre et son comportement et une classe inactive UML est traduite par un type de record en Fiacre. Afin d'établir des règles de transformation, on a proposé deux approches qui permettent de les valider : 1. Montrer la préservation des propriétés lors des transformations en Fiacre. 2. Montrer l'équivalence des sémantiques d'exécution entre le monde UML et le monde Fiacre

Model Driven Communication Protocol Engineering and Simulation based Performance Analysis using UML 2.0

The automated functional and performance analysis of communication systems specified with some Formal Description Technique has long been the goal of telecommunication engineers. In the past SDL and Petri nets have been the most popular FDTs for the purpose. With the growth in popularity of UML the most obvious question to ask is whether one can translate one or more UML diagrams describing a system to a performance model. Until the advent of UML 2.0, that has been an impossible task since the semantics were not clear. Even though the UML semantics are still not clear for the purpose, with UML 2.0 now released and using ITU recommendation Z.109, we describe in this dissertation a methodology and tool called proSPEX (protocol Software Performance Engineering using XMI), for the design and performance analysis of communication protocols specified with UML. Our first consideration in the development of our methodology was to identify the roles of UML 2.0 diagrams in the performance modelling process. In addition, questions regarding the specification of non-functional duration contraints, or temporal aspects, were considered. We developed a semantic time model with which a lack of means of specifying communication delay and processing times in the language are addressed. Environmental characteristics such as channel bandwidth and buffer space can be specified and realistic assumptions are made regarding time and signal transfer. With proSPEX we aimed to integrate a commercial UML 2.0 model editing tool and a discrete-event simulation library. Such an approach has been advocated as being necessary in order to develop a closer integration of performance engineering with formal design and implementation methodologies. In order to realize the integration we firstly identified a suitable simulation library and then extended the library with features required to represent high-level SDL abstractions, such as extended finite state machines (EFSM) and signal addressing. In implementing proSPEX we filtered the XML output of our editor and used text templates for code generation. The filtering of the XML output and the need to extend our simulation library with EFSM abstractions was found to be significant implementation challenges. Lastly, in order to to illustrate the utility of proSPEX we conducted a performance analysis case-study in which the efficient short remote operations (ESRO) protocol is used in a wireless e-commerce scenario

Real Time System Development with UML: A Case Study

In this thesis we look at the challenges regarding VoIP and to the developer of an application providing this service. We explore CASE tools that can be used to model and verify the design of a VoIP application. VoIP applications will not be accepted by the market unless it is able to provide an audio quality comparable to traditional phones. The voice module of the application that we analyse initially did not meet these requirements. We investigate how the design and implementation must be altered to meet them. Although UML in its current specification is not adapted to the design of real-time applications, CASE tools exist that propose an extension of UML for this purpose. We investigate two of these - Rational Rose RT and Telelogic Tau - for their usefulness in re-engineering the application. We show their support partially covers our needs and we present novel UML concepts that would have been useful in resolving our task. We further demonstrate important new concepts of UML 2.0

Applications Based on Generator of Test Cases

Cílem této bakalářské práce je vytvořit přehled aktuálního stavu nástrojů, které umožňují automaticky generovat testovací případy. Dále na příkladu zvoleného nástroje ukázat způsob práce s ním a jeho schopnosti v generaci spustitelných testu. Pro následující práci byl vybrán nástroj UPPAAL, který umožňuje vytvořit model zvoleného systému pomocí časovaných automatů, ověřit a simulovat jeho běh a následně vytvořit testovací případ pro daný systém. Ve výsledku nástroj vygeneruje cestu průchodu systémem, kterou je možné uložit ve formě spustitelného testovacího případu a to v libovolném programovacím jazyce. Pro testování byly zvoleny tři různé systémy: systém vypínače světla, implementovaný v jazyce Java; 2-bitová násobička, jejíž chování je popsané pomocí jazyka Verilog; a systém zjednodušeného výtahu, který je představen v jazyce C. Ve výsledku byly získány spustitelné testovací případy pro zvolené systémy, spolu s jejich vlastnostmi jako pokrytí systému, počet kroků pro dosažení cílů a kvalita vygenerovaných cest.The aim of this bachelor's thesis is to create an overview of the current state of tools that allow automatic generation of test cases and select one tool to show how it works and its ability to generate executable tests. The UPPAAL program was chosen for the following work. Tool allows to create a model of the selected system using timed automata, verify and simulate its operation and create a test case for the system. In the results, the tool generates a path through the system, which can be saved in the form of executable test cases in any programming language. Three different systems were chosen for testing: a light switch system implemented in Java; 2-bit multiplier, which behavior is described by Verilog language; and a simplified elevator system, which working process is introduced in C language. As a result, executable test cases were obtained for selected systems along with their features such as system coverage, number of steps to achieve goals, and quality of generated paths.