On-die CMOS temperature sensors

Temperature changes can have an impact on the reliability and functioning of sensitive integrated circuits. In this thesis an analog DTMOS transistor temperature was designed and laid out in 22 nm CMOS fabrication process using Cadence Virtuoso electrical design automation suite. The design was verifed and validated using Cadence Spectre electrical simulation software and the simulation results were analyzed and compared to previous sensor designs. The new design was found to be less power hungry but slightly less accurate than the original design. The new design also showed a signifcant improvement in operating voltage resilience compared to a previous design used at LG Electronics Finland Lab Oy. Over all the design goals were met and the sensor is ready to be added to be a part of a future integrated circuit

공정 변화에 둔감한 자동 온도 보상 셀프 리프레쉬용 모바일 디램 온도계

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2013. 8. 김수환.Smaller transistors mean that capacitors are charged less uniformly, which increases the self-refresh current in the DRAMs used in mobile devices. Adaptive self-refresh using an on-chip thermometer can solve this problem. In this thesis, a PVT tolerant on-chip CMOS thermometer specifically designed for controlling the refresh period of a DRAM will be proposed for low power mobile DRAM. Two types of on-chip CMOS thermometer including a novel temperature sensor is proposed, which is implemented in two different DRAM process technologies integrated into mobile LPDDR2 and LPDDR3 products. The on-chip thermometer incorporating in mobile LPDDR2 chip is fabricated in a 44nm DRAM process with a supply of 1.1V. The sensor has a temperature sensitivity of −3.2mV/°C, over a range of 0°C to 110°C. Its resolution is 1.94°C and is only limited by the 6.2mV step of the associated resistor ladder not by its own design. The high linearity of the sensor permits one-point calibration, after which the errors in 61 sample circuits ranged between −1.42°C and +2.66°C. The sensor has an active area of 0.001725mm2 and consumes less than 0.36μW on average with a supply of 1.1V. To improve the overall performance including ultra-low operation voltage, temperature sensitivity, low power consumption, high linearity regardless of process skew variations and high productivity improved by one point calibration, the folded type on-chip thermometer incorporating in mobile LPDDR3 chip which fabricated in a 29nm DRAM process with a supply of 1.1V and 0.8V will be proposed. This folded type sensor exhibits further upgrading properties such as a temperature sensitivity of −3.2mV/°[email protected] &−3.13mV/°C @0.8V, over wide range of -40°C to 110°C. Its resolution is 1.85°[email protected] & 1.98°[email protected] and is only limited by the 6.2mV step. The more linearity of folded type sensor permits one-point calibration, after which the errors in 494 sample circuits ranged between −1.94°C and +1.61°C. The folded type sensor has an active area of 0.001606mm2 and consumes less than 0.19μ[email protected] & 0.14μ[email protected] on average slightly more than unfolded type sensor.ABSTRACT I CONTENTS III LIST OF FIGURES V LIST OF TABLES IX CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 3 CHAPTER 2 ARCHITECTURE OF THERMOMETER 5 2.1 INTRODUCTION TO ON-CHIP THERMOMETER IN MOBILE DRAM 5 2.2 PROPOSED ON-CHIP CMOS THERMOMETER ARCHITECTURE 17 2.3 TEMPERATURE READOUT PROCEDURE OF PROPOSED ON-CHIP CMOS THERMOMETER 23 2.4 PROPOSED FOLDED TYPE ON-CHIP CMOS THERMOMETER ARCHITECTURE 25 2.5 TEMPERATURE READOUT PROCEDURE OF PROPOSED FOLDED TYPE ON-CHIP CMOS THERMOMETER 30 2.6 ONE-POINT CALIBRATION METHOD 32 2.7 TEMPERATURE LINEARITY OF TEMPERATURE SENSOR 35 CHAPTER 3 OPERATIONAL PRINCIPLES OF CMOS TEMPERATURE SENSOR IN MOBILE DRAM 39 3.1 PRIOR WORKS OF ON-CHIP THERMOMETER 39 3.2 PROPOSED CMOS TEMPERATURE SENSOR IN MOBILE DRAM 44 3.3 OPERATION PRINCIPLES OF PROPOSED TEMPERATURE SENSOR 48 3.4 PROPOSED FOLDED TYPE TEMPERATURE SENSOR 55 CHAPTER 4 PERIPHERAL CIRCUITS OF THERMOMETER 60 4.1 REGULATOR FOR VLTCSR SUPPLY 61 4.1.1 DC ANALYSIS 62 4.1.2 AC ANALYSIS 63 4.2 RESISTOR DECK 67 4.3 COMPARATOR 68 CHAPTER 5 EXPERIMENTAL RESULTS 70 5.1 ON-CHIP CMOS THERMOMETER IN 44NM CMOS PROCESS FOR MOBILE LPDDR2 74 5.2 FOLDED TYPE ON-CHIP CMOS THERMOMETER IN 29NM CMOS PROCESS FOR MOBILE LPDDR3 77 CHAPTER 6 CONCLUSIONS 83 BIBLIOGRAPHY 86 ABSTRACT IN KOREAN 89Docto

New Possibilities In Low-voltage Analog Circuit Design Using Dtmos Transistors

(Doktora) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2013(PhD) -- İstanbul Technical University, Institute of Science and Technology, 2013Bu çalışmada DTMOS yaklaşımı çok düşük besleme gerilimlerinde çalışan çok düşük güç tüketimli devrelere başarıyla uygulanmıştır. Tasarlanan devreler arasında OTA, OP-AMP, CCII gibi analog aktif yapı blokları, çarpma devresi, sadece-MOS yapılar gibi devreler bulunmaktadır. Tasarlanan devreler SPICE benzetimleri ile doğrulanmıştır. İleri yönde gövde kutuplamaya bağlı olarak DTMOS transistorun yapısından kaynaklanan, efektif olarak düşük eşik gerilimli çalışma özelliği nedeniyle, çok düşük güç tüketimli ve çok düşük gerilimli devrelerde DTMOS yaklaşımının geçerli bir alternatif olduğu bu çalışmayla gösterilmiştir. DTMOS yaklaşımının geniş bir alanda çeşitlilik gösteren analog devre yapılarında çok düşük besleme gerilimlerinde bile kabul edilebilir bir performansla kullanılabileceği bulunmuştur.In this study, DTMOS approach to the design of ultra low-voltage and ultra low-power analog circuits, has been successfully applied to the circuits ranging from EEG filtering circuits, speech processing filters in hearing aids, multipliers, analog active building blocks: OTA, OP-AMP, CCII to MOS-only circuits. The proposed circuits are verified with SPICE simulations. It is found that in designing ultra low-voltage, ultra low-power analog circuits, DTMOS approach is a viable alternative due to its inherent characteristic of effective low threshold voltage behaviour under forward body bias. This approach can be applied to several analog application subjects with acceptable performance under even ultra low supply voltages.DoktoraPh

Analog and mixed-signal design and test techniques for improved reliability

The relentless evolution of semiconductor technology has led to a pervasive reliance on integrated circuits (ICs) across an array of applications, from consumer electronics to safety-critical systems in automotive and medical devices. Ensuring the reliability and robustness of these ICs has become paramount. This dissertation addresses the growing need for defect-oriented testing in analog and mixed-signal (AMS) circuits, introducing a novel digital-like methodology. It emphasizes breaking down complex AMS circuits into smaller, manageable subcircuits, which are rigorously examined using purely digital monitors and injectors. The methodology is resource-efficient, optimizing existing circuit resources to minimize area overhead and power consumption. A significant achievement lies in the development of a Built-In Self-Test (BIST) for a 12-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC), showcasing the approach's effectiveness and flexibility. Additionally, this dissertation pioneers a smart sensor design approach that reduces dependence on intricate device models, thereby ensuring high performance across a broad range of operating conditions. A case study on a temperature-to-digital converter (TDC) design demonstrates its capability to function reliably over an extensive temperature range. The methodology optimizes parameters, allowing energy-efficient sensor designs that meet industry standards while minimizing silicon area and power consumption. These works signify a dedicated commitment to advancing the reliability and functional safety of analog and mixed-signal circuits, contributing to the evolving landscape of IC design