Low-cost duplication for separable error detection in computer arithmetic

Low-cost arithmetic error detection will be necessary in the future to ensure correct and safe system operation. However, current error detection mechanisms for arithmetic either have high area and energy overheads or are complex and offer incomplete protection against errors. Full duplication is simple, strong, and separable, but often is prohibitively costly. Alternative techniques such as arithmetic error coding require lower hardware and energy overheads than full duplication, but they do so at the expense of high design effort and error coverage holes. The goal of this research is to mitigate the deficiencies of duplication and arithmetic error coding to form an error detection scheme that may be readily employed in future systems. The techniques described by this work use a general duplication technique that employs an alternate number system in the duplicate arithmetic unit. These novel dual modular redundancy organizations are referred to as low-cost duplication, and they provide compelling efficiency and coverage advantages over prior arithmetic error detection mechanisms.Electrical and Computer Engineerin

A Solder-Defined Computer Architecture for Backdoor and Malware Resistance

This research is about securing control of those devices we most depend on for integrity and confidentiality. An emerging concern is that complex integrated circuits may be subject to exploitable defects or backdoors, and measures for inspection and audit of these chips are neither supported nor scalable. One approach for providing a “supply chain firewall” may be to forgo such components, and instead to build central processing units (CPUs) and other complex logic from simple, generic parts. This work investigates the capability and speed ceiling when open-source hardware methodologies are fused with maker-scale assembly tools and visible-scale final inspection. The author has designed, and demonstrated in simulation, a 36-bit CPU and protected memory subsystem that use only synchronous static random access memory (SRAM) and trivial glue logic integrated circuits as components. The design presently lacks preemptive multitasking, ability to load firmware into the SRAMs used as logic elements, and input/output. Strategies are presented for adding these missing subsystems, again using only SRAM and trivial glue logic. A load-store architecture is employed with four clock cycles per instruction. Simulations indicate that a clock speed of at least 64 MHz is probable, corresponding to 16 million instructions per second (16 MIPS), despite the architecture containing no microprocessors, field programmable gate arrays, programmable logic devices, application specific integrated circuits, or other purchased complex logic. The lower speed, larger size, higher power consumption, and higher cost of an “SRAM minicomputer,” compared to traditional microcontrollers, may be offset by the fully open architecture—hardware and firmware—along with more rigorous user control, reliability, transparency, and auditability of the system. SRAM logic is also particularly well suited for building arithmetic logic units, and can implement complex operations such as population count, a hash function for associative arrays, or a pseudorandom number generator with good statistical properties in as few as eight clock cycles per 36-bit word processed. 36-bit unsigned multiplication can be implemented in software in 47 instructions or fewer (188 clock cycles). A general theory is developed for fast SRAM parallel multipliers should they be needed

Optimisation des chemins de données arithmétiques par l'utilisation des systèmes de numération redondants

This thesis presents the optimization of arithmetic data paths with the automatic integration of redundant notation system in the flow of VLSI design, so as to make it more accessible. The work is cut into two phases.The first objective is to incorporate redundant and mixed operators and expertise related to their use in the synthesis low. The good intrinsic performance of these operators indicate the potential value of this approach. Three optimization algorithms are proposed, based on the redefinition of sequences between arithmetic operators.The second is devoted to the development of the design environment in which will be used these algorithms. This environment meets the arithmetic-related needs and provides a circuit description language with a high level of abstraction. These algorithms have been applied to different arithmetic circuits and the results confirm that the automatic integration of redundant arithmetic significantly improves performance compared to a conventional layout of these circuits.Cette thèse présente l’optimisation des chemins de données arithmétiques par l’intégration automatique du système des notations redondantes dans le flot de conception VLSI, de façon à le rendre plus accessible. Les travaux effectués se découpent en deux phases.La première a pour objectif d’incorporer les opérateurs redondants et mixtes et le savoir-faire lié à leur usage dans la synthèse bas niveau. Les bonnes performances intrinsèques de ces opérateurs montrent l’intérêt potentiel d’une telle approche. Trois algorithmes d’optimisation sont proposés, basés sur la redéfinition des enchaînements entre opérateurs arithmétiques. La seconde est consacrée à la mise en place de l’environnement de conception dans lequel seront utilisés ces algorithmes. Cet environnement répond aux besoins liés à l’arithmétique et fournit un langage de description de circuits ayant un haut niveau d’abstraction. Ces algorithmes ont été appliqués sur différents circuits arithmétiques et les résultats obtenus confirment que l’intégration automatique de l’arithmétique redondante améliore nettement les performances par rapport à une implantation classique de ces circuits