회로의 1차원 배치문제 해결을 위한 새로운 지역최적화 알고리즘

학위논문(석사) -- 서울대학교대학원 : 공과대학 컴퓨터공학부, 2023. 2. 이재진.Area reduction is one of the most critical objectives in semiconductor design since it improves profitability due to increasing net die per wafer. Although there exist various commercial tools, memory design requires the full custom design flow to reduce the area because the place and route (P&R) functionality in the tools are not effective in the dram design flow. Furthermore, one-dimensional (1D) layout is indispensable due to the presence of peripheral regions. Inspired by the above, we propose a new framework to minimize the wire length in the standard cells 1D layout. The framework consists of the heuristic algorithm, which efficiently places standard cells to minimize the overall wire length of a 1D unit block composed of multiple standard cells and a Clustering algorithm. Through the cooperation of three algorithms, it obtains the 26.6% improved total wire length on 502 units consisting of 3 to 98 standard cells designed by human experts.면적 감소는 웨이퍼당 Netdie 증가로 수익성을 높이기 때문에 반도체 설계에서 가장 중요한 목표 중 하나이다. ASIC 설계를 위한 면적 최적화를 지원하는 다수의 상업용 툴이 존재하지만, 메모리 설계 분야에서는 Full Custom Design Flow를 이용해서 chip의 면적을 줄이고 있다. 이는 설계 관련 데이터에 대한 공유를 엄격히 제한하는 메모리 설계 회사의 보안 규정으로 인해, 상용 툴 제작 업체가 메모리 설계 분야에 관련된 최적화 툴을 개발하지 못했음에 기인한다. 특히, 메모리의 Peripheral 영역을 설계하기 위해서 표준 셀을 1차원(1D)으로 배치하는 절차가 존재하는데, 이 또한 지원하는 툴이 없는 실정이다. 위의 내용에서 영감을 받아 표준 셀의 1차원 배치를 위한 레이아웃에서 와이어 길이를 최소화하는 새로운 프레임워크를 제안한다. 표준 셀을 1차원으로 배치하기 위한 프레임워크는 다음과 같은 알고리즘으로 구성되는데, 여러 표준 셀로 구성된 1D 단위 블록의 전체 와이어 길이를 최소화하기 위해 표준 셀을 효율적으로 배치하는 휴리스틱 알고리즘, Clustering 알고리즘 및 클럭 제거-재구성 알고리즘이 프레임워크의 그 핵심이다. 이 세 가지 알고리즘을 적용함으로써, 전문가들이 설계한, 3~98개의 표준 셀로 구성된 502개 유닛 블록의 총 와이어 길이를 27.97% 개선하는 성과를 달성했다.Chapter 1. Introduction １ Chapter 2. Related Work ３ Chapter 3. Contributions ４ Chapter 4. Problem Definition ５ Chapter 5. Methodology ７ 5.1. Structure of Genetic Algorithm ８ 5.2 MultiStart ９ 5.3 Greedy-K: New Local Optimization Algorithm ９ 5.4 Clustering for 1D Placement Problems １１ 5.5 Cell Flipping １４ 5.7 DFS&BFS Initialization １５ Chapter 6 Experimental Results １７ 6.1 Test Environment and Condition １７ 6.2 Performance of DFS&BFS Initialization １８ 6.3 Performance of Cell Flipping １８ 6.4 GA vs. Greedy-K vs. GA+Greedy-K １９ 6.5 Human Experts vs. Cell Flipping vs. Clustering ２１ 6.6 Parallel Processing ２２ Chapter 7 Conclusion ２４석

Power tests of a string of magnets comprising a full cell of the Superconducting Super Collider

In this paper we describe the operation and testing of a string of magnets comprising a full cell of the Superconducting Super Collider (SSC). The full cell configuration composed of ten dipoles, two quadrupoles, and three spool pieces is the longest SSC magnet string ever tested. Although the tests of the full cell were undertaken after the SSC project was marked for termination, their completion was deemed necessary and useful to future efforts at other accelerator laboratories utilizing Superconducting magnets. The focus of this work is on the electrical and cryogenic performance of the string components and the quench protection system with an emphasis on solving some of the questions concerning electrical performance raised during the previous two experimental runs involving a half cell configuration

Third International Symposium on Magnetic Suspension Technology

In order to examine the state of technology of all areas of magnetic suspension and to review recent developments in sensors, controls, superconducting magnet technology, and design/implementation practices, the Third International Symposium on Magnetic Suspension Technology was held at the Holiday Inn Capital Plaza in Tallahassee, Florida on 13-15 Dec. 1995. The symposium included 19 sessions in which a total of 55 papers were presented. The technical sessions covered the areas of bearings, superconductivity, vibration isolation, maglev, controls, space applications, general applications, bearing/actuator design, modeling, precision applications, electromagnetic launch and hypersonic maglev, applications of superconductivity, and sensors

Defect-based testing of LTS digital circuits

A Defect-Based Test (DBT) methodology for Superconductor Electronics (SCE) is presented in this thesis, so that commercial production and efficient testing of systems can be implemented in this technology in the future. In the first chapter, the features and prospects for SCE have been presented. The motivation for this research and the outline of the thesis were also described in Chapter 1. It has been shown that high-end applications such as Software-Defined Radio (SDR) and petaflop computers which are extremely difficult to implement in top-of-the-art semiconductor technologies can be realised using SCE. But, a systematic structural test methodology had yet to be developed for SCE and has been addressed in this thesis. A detailed introduction to Rapid Single-Flux Quantum (RSFQ) circuits was presented in Chapter 2. A Josephson Junction (JJ) was described with associated theory behind its operation. The JJ model used in the simulator used in this research work was also presented. RSFQ logic with logic protocols as well as the design and implementation of an example D-type flip-flop (DFF) was also introduced. Finally, advantages and disadvantages of RSFQ circuits have been discussed with focus on the latest developments in the field. Various techniques for testing RSFQ circuits were discussed in Chapter 3. A Process Defect Monitor (PDM) approach was presented for fabrication process analysis. The presented defect-monitor structures were used to gather measurement data, to find the probability of the occurrence of defects in the process which forms the first step for Inductive Fault Analysis (IFA). Results from measurements on these structures were used to create a database for defects. This information can be used as input for performing IFA. "Defect-sprinkling" over a fault-free circuit can be carried out according to the measured defect densities over various layers. After layout extraction and extensive fault simulation, the resulting information will indicate realistic faults. In addition, possible Design-for-Testability (DfT) schemes for monitoring Single-Flux Quantum (SFQ) pulses within an RSFQ circuit has also been discussed in Chapter 3. The requirement for a DfT scheme is inevitable for RSFQ circuits because of their very high frequency of operation and very low operating temperature. It was demonstrated how SFQ pulses can be monitored at an internal node of an SCE circuit, introducing observability using Test-Point Insertion (TPI). Various techniques were discussed for the introduction of DfT and to avoid the delay introduced by the DfT structure if it is required. The available features in the proposed design for customising the detector make it attractive for a detailed DBT of RSFQ circuits. The control of internal nodes has also been illustrated using TPI. The test structures that were designed and implemented to determine the occurrence of defects in the processes can also be used to locate the position for the insertion of the above mentioned DfT structures

The CMS experiment at the CERN LHC

The Compact Muon Solenoid (CMS) detector is described. The detector operates at the Large Hadron Collider (LHC) at CERN. It was conceived to study proton-proton (and leadlead) collisions at a centre-of-mass energy of 14 TeV (5.5 TeV nucleon-nucleon) and at luminosities up to 1034 cm-2s-1 (1027 cm-2s-1). At the core of the CMS detector sits a high-magnetic field and large-bore superconducting solenoid surrounding an all-silicon pixel and strip tracker, a lead-tungstate scintillating-crystals electromagnetic calorimeter, and a brass-scintillator sampling hadron calorimeter. The iron yoke of the flux-return is instrumented with four stations of muon detectors covering most of the 4π solid angle. Forward sampling calorimeters extend the pseudorapidity coverage to high values (|η| ≤ 5) assuring very good hermeticity. The overall dimensions of the CMS detector are a length of 21.6 m, a diameter of 14.6 m and a total weight of 12500 t

NASA SBIR abstracts of 1991 phase 1 projects

The objectives of 301 projects placed under contract by the Small Business Innovation Research (SBIR) program of the National Aeronautics and Space Administration (NASA) are described. These projects were selected competitively from among proposals submitted to NASA in response to the 1991 SBIR Program Solicitation. The basic document consists of edited, non-proprietary abstracts of the winning proposals submitted by small businesses. The abstracts are presented under the 15 technical topics within which Phase 1 proposals were solicited. Each project was assigned a sequential identifying number from 001 to 301, in order of its appearance in the body of the report. Appendixes to provide additional information about the SBIR program and permit cross-reference of the 1991 Phase 1 projects by company name, location by state, principal investigator, NASA Field Center responsible for management of each project, and NASA contract number are included

RESISTIVE RAM BASED MAIN-MEMORY SYSTEMS: UNDERSTANDING THE OPPORTUNITIES, LIMITATIONS, AND TRADEOFFS

As DRAM faces scaling issues as a high-density memory, emerging technologies are being explored as alternatives. One promising candidate is Resistive Memories (ReRAM), which is scalable, vertically stackable, and because of the possibility of integration with standard logic process, can deliver higher density as a main-memory solution. The key differentiator with this approach involves a ReRAM memory array that integrates directly with a logic processor underneath. In this research work, I explore ReRAM as a main-memory alternative at three levels of detail – at the device level, the physical-design level, and finally at the architecture level. I begin with an overview of ReRAM and compare with alternate technologies. I look at the physical design of the solution and present the results of area studies on integrating a VSCALE processor at the 45nm technology node with a ReRAM bit-cell array. The area study was performed based on parameters specified by my collaborators at Crossbar Inc. The results showed that the optimum operating point is at 50% array efficiency with a VSCALE processor, and that this configuration incurs an area penalty of 18%. Two of the key challenges for ReRAM with respect to DRAM performance include the higher write latency requirement (typically on the order of 1us) and the lower write endurance (typically less than 10^8 cycles). This compares with DRAM write-latency times of less than 30ns (depending on technology node and generation) and write endurance of more than 10^15 write cycles. In this research work, I explore the possibility of utilizing the ReRAM cell in an intermediate state between non-volatile state and threshold state, where I intentionally tradeoff the write energy for a much lower data retention. This allows the chip to more easily replace existing DRAM-like main memory applications, without requiring higher write programming current or accommodating for a longer write latency. I performed this evaluation both at the device-level and at the architecture level. At the device-level, I used UMD’s Nano-fab lab to construct a Metal-Oxide based ReRAM bitcells on which I characterized the relationship between data-retention and write current applied. My fabricated ReRAM was composed of Titanium-Oxide and Aluminum Oxide. I also confirmed the behavior of a mixed-volatility state where a formed filament relaxes over time to move to a high-resistance level. Based on my experimental measurements, operating in the mixed volatile state would reduce write energy by 10 to 100x, and thereby improve the write endurance. Finally, at the architecture-level, I used the Structural Simulation Toolkit (SST) to characterize a ReRAM-based main-memory system and compare with a DRAM-based one using our research group’s DRAMSIM3 tool. I also characterized the sensitivity of various architectural parameters (core-to-memory controller ratio, queue depth, NoC topology) on system performance on stream and gups-based graph benchmarks which indicated that the torus topology will provide reasonable performance. Impact of the number of parallel processors indicated that at low processor counts, DRAM outperforms ReRAM due to its faster memory latency. However, at high processor counts, ReRAM with its higher number of parallel connections is able to deliver higher system performance than DRAM