Switching techniques for broadband ISDN

The properties of switching techniques suitable for use in broadband networks have been investigated. Methods for evaluating the performance of such switches have been reviewed. A notation has been introduced to describe a class of binary self-routing networks. Hence a technique has been developed for determining the nature of the equivalence between two networks drawn from this class. The necessary and sufficient condition for two packets not to collide in a binary self-routing network has been obtained. This has been used to prove the non-blocking property of the Batcher-banyan switch. A condition for a three-stage network with channel grouping and link speed-up to be nonblocking has been obtained, of which previous conditions are special cases. A new three-stage switch architecture has been proposed, based upon a novel cell-level algorithm for path allocation in the intermediate stage of the switch. The algorithm is suited to hardware implementation using parallelism to achieve a very short execution time. An array of processors is required to implement the algorithm The processor has been shown to be of simple design. It must be initialised with a count representing the number of cells requesting a given output module. A fast method has been described for performing the request counting using a non-blocking binary self-routing network. Hardware is also required to forward routing tags from the processors to the appropriate data cells, when they have been allocated a path through the intermediate stage. A method of distributing these routing tags by means of a non-blocking copy network has been presented. The performance of the new path allocation algorithm has been determined by simulation. The rate of cell loss can increase substantially in a three-stage switch when the output modules are non-uniformly loaded. It has been shown that the appropriate use of channel grouping in the intermediate stage of the switch can reduce the effect of non-uniform loading on performance

Performance analysis of virtual path over large-scale ATM switches.

by Tang Oo.Thesis submitted in: December 1997.Thesis (M.Phil.)--Chinese University of Hong Kong, 1998.Includes bibliographical references (leaves 68-[75]).Abstract also in Chinese.Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Background --- p.1Chapter 1.2 --- The Concept of Cross-Path Switching --- p.8Chapter 1.3 --- Contribution and Organization of Thesis --- p.12Chapter 2 --- The Virtual Path Scheduling Scheme --- p.14Chapter 2.1 --- The Trade-off Between Throughput and Concentration Loss --- p.14Chapter 2.2 --- Partition of Virtual Paths --- p.19Chapter 2.3 --- The Capacity and Route Assignment of Virtual Paths --- p.21Chapter 3 --- Performance Analysis and Simulation Results --- p.28Chapter 3.1 --- The Improvement of Concentration Loss --- p.28Chapter 3.2 --- The Throughput with Look-ahead Scheme --- p.30Chapter 3.3 --- The Throughput with Input Smoothing Scheme --- p.34Chapter 3.4 --- The Throughput with Bursty Source --- p.37Chapter 3.5 --- Buffer Dimensioning and The Cell Loss Probability Due to Buffer Overflow --- p.38Chapter 4 --- Capacity Assignment and Evaluation of Multiplexing Gain --- p.47Chapter 4.1 --- Principle of Capacity Assignment --- p.47Chapter 4.2 --- The Model of Virtual Path --- p.49Chapter 4.3 --- Capacity Assignment for CBR Service --- p.51Chapter 4.4 --- Capacity Assignment for Real-time VBR Service --- p.53Chapter 4.5 --- Capacity Assignment for Non Real-time VBR Service --- p.55Chapter 4.6 --- Capacity Matrix --- p.56Chapter 4.7 --- The Evaluation of Multiplexing Gain of Input Stage --- p.58Chapter 5 --- Discussions and Conclusions --- p.64Bibliography --- p.6

Architectures of new switching systems.

by Lam Wan.Thesis submitted in: November 1997.Thesis (M.Phil.)--Chinese University of Hong Kong, 1998.Includes bibliographical references (leaves 96-102).Abstract also in Chinese.Part IChapter 1 --- Introduction to Integrated Intelligent Personal Communication System --- p.1Chapter 2 --- The Switching Architecture --- p.5Chapter 2.1 --- The Overall Switching Architecture --- p.6Chapter 2.2 --- Switching Module --- p.10Chapter 2.2.1 --- Traffic Routing in Switching Module --- p.11Chapter 2.2.2 --- Structure of Switching Module --- p.15Chapter 2.2.3 --- Wireless Base Interface --- p.16Chapter 2.2.4 --- Trunk Interface --- p.18Chapter 2.2.5 --- Analog Interfaces --- p.18Chapter 2.3 --- Network Intelligence --- p.19Chapter 2.4 --- Wireless Part --- p.21Chapter 2.4.1 --- Call-Setup in IIPCS --- p.24Chapter 2.4.2 --- Handoff --- p.25Chapter 2.4.3 --- Wireless Base --- p.27Chapter 2.5 --- Downstream Wired Extensions --- p.28Chapter 2.6 --- Upstream Wired Part --- p.28Chapter 2.7 --- Voice System --- p.28Chapter 2.8 --- Features of the IIPCS --- p.29Chapter 3 --- Concluding Remarks --- p.33Chapter 3.1 --- Summary --- p.35Chapter 3.2 --- Directions for Further Research --- p.36Part IIChapter 4 --- Introduction to Next-Generation Switch --- p.37Chapter 5 --- Architecture of Next-Generation Switch --- p.41Chapter 5.1 --- Overall Architecture of Next-Generation Switch --- p.42Chapter 5.1.1 --- Interface module --- p.44Chapter 5.1.2 --- Packetizer --- p.46Chapter 5.2 --- Concentration Fabric --- p.50Chapter 5.3 --- Shared-Buffer Memory Switch --- p.53Chapter 6 --- Concentration Networks --- p.56Chapter 6.1 --- Background of Concentration Networks --- p.56Chapter 6.2 --- k-Sorting --- p.63Chapter 6.3 --- Concentrator --- p.72Chapter 6.3.1 --- Nk-to-k Concentrator --- p.73Chapter 6.3.2 --- Match between Circles with Cost Reduction --- p.75Chapter 6.4 --- The Structure of a Molecule --- p.78Chapter 6.5 --- Summary --- p.81Chapter 7 --- Lock-Latch Algorithm --- p.82Chapter 8 --- Performance Evaluation --- p.88Chapter 9 --- Concluding Remarks --- p.93Chapter 9.1 --- LSI Implementation --- p.94Chapter 9.2 --- Summary --- p.95Bibliograph

Performance study of multirate circuit switching in quantized clos network.

by Vincent Wing-Shing Tse.Thesis submitted in: December 1997.Thesis (M.Phil.)--Chinese University of Hong Kong, 1998.Includes bibliographical references (leaves 62-[64]).Abstract also in Chinese.Chapter 1 --- Introduction --- p.1Chapter 2 --- Principles of Multirate Circuit Switching in Quantized Clos Network --- p.10Chapter 2.1 --- Formulation of Multirate Circuit Switching --- p.11Chapter 2.2 --- Call Level Routing in Quantized Clos Network --- p.12Chapter 2.3 --- Cell Level Routing in Quantized Clos Network --- p.16Chapter 2.3.1 --- Traffic Behavior in ATM Network --- p.17Chapter 2.3.2 --- Time Division Multiplexing in Multirate Circuit Switching and Cell-level Switching in ATM Network --- p.19Chapter 2.3.3 --- Cell Transmission Scheduling --- p.20Chapter 2.3.4 --- Capacity Allocation and Route Assignment at Cell-level --- p.29Chapter 3 --- Performance Evaluation of Different Implementation Schemes --- p.31Chapter 3.1 --- Global Control and Distributed Switching --- p.32Chapter 3.2 --- Implementation Schemes of Quantized Clos Network --- p.33Chapter 3.2.1 --- Classification of Switch Modules --- p.33Chapter 3.2.2 --- Bufferless Switch Modules Construction Scheme --- p.38Chapter 3.2.3 --- Buffered Switch Modules Construction Scheme --- p.42Chapter 3.3 --- Complexity Comparison --- p.44Chapter 3.4 --- Delay Performance of The Two Implementation Schemes --- p.47Chapter 3.4.1 --- Assumption --- p.47Chapter 3.4.2 --- Simulation Result --- p.50Chapter 4 --- Conclusions --- p.59Bibliography --- p.6

Analysis of generic discrete-time buffer models with irregular packet arrival patterns

De kwaliteit van de multimediadiensten die worden aangeboden over de huidige breedband-communicatienetwerken, wordt in hoge mate bepaald door de performantie van de buffers die zich in de diverse netwerkele-menten (zoals schakelknooppunten, routers, modems, toegangsmultiplexers, netwerkinter- faces, ...) bevinden. In dit proefschrift bestuderen we de performantie van een dergelijke buffer met behulp van een geschikt stochastisch discrete-tijd wachtlijnmodel, waarbij we het geval van meerdere uitgangskanalen en (niet noodzakelijk identieke) pakketbronnen beschouwen, en de pakkettransmissietijden in eerste instantie één slot bedragen. De grillige, of gecorreleerde, aard van een pakketstroom die door een bron wordt gegenereerd, wordt gekarakteriseerd aan de hand van een algemeen D-BMAP (discrete-batch Markovian arrival process), wat een generiek kader creëert voor het beschrijven van een superpositie van dergelijke informatiestromen. In een later stadium breiden we onze studie uit tot het geval van transmissietijden met een algemene verdeling, waarbij we ons beperken tot een buffer met één enkel uitgangskanaal. De analyse van deze wachtlijnmodellen gebeurt hoofdzakelijk aan de hand van een particuliere wiskundig-analytische aanpak waarbij uitvoerig gebruik gemaakt wordt van probabiliteitsgenererende functies, die er toe leidt dat de diverse performantiematen (min of meer expliciet) kunnen worden uitgedrukt als functie van de systeemparameters. Dit resul-teert op zijn beurt in efficiënte en accurate berekeningsalgoritmen voor deze grootheden, die op relatief eenvoudige wijze geïmplementeerd kunnen worden

Interworking public and private ATM networks

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1996.Includes bibliographical references (p. 125-128).by C. Brit Gould.M.Eng

Isochronets: A High-speed Network Switching Architecture

Traditional network architectures present two main limitations when applied to High- Speed Networks (HSNs): they do not scale with link speeds and they do not adequately support the Quality of Service (QoS) needs of high-performance applications. This thesis introduces the Isochronets architecture that overcomes both limitations. Isochronets view frame motions over links in analogy to motions on roads. In the latter, traffic lights can synchronize to create green waves of uninterrupted motion. Isochronets accomplish similar uninterrupted motion by periodically configuring network switches to create end-to-end routes in the network. Frames flow along these routes with no required header processing at intermediate switches. Isochronets offer several advantages. First, they are scaleable with respect to transmission speeds. Switches merely configure routes on a time scale that is significantly longer than and independent of the average frame transmission time. Isochronets do not require frame processing and thus avoid conversions from optical to electronic representations. They admit efficient optical transmissions under electronically controlled switches. Second, Isochronets ensure QoS for high-performance applications in terms of latency, jitter, loss, and other service qualities. Isochronet switches can give priority to frames arriving from selected links. At one extreme, they may give a source the right-of-way to the destination by assigning priority to all links in its path. Additionally, other sources may still transmit at lower priority. At the other extreme, they may give no priority to sources and frames en route to the same destination contend for intermediate links. In between, Isochronets can accomplish a myriad of priority allocations with diverse QoS. Third, Isochronets can support multiple protocols without adaptation between different frame structures. End nodes view the network as a media access layer that accepts frames of arbitrary structure. The main contributions of this thesis are: Design of the Isochronets architecture. Design and implementation of a gigabit per second Isochronet switch (Isoswitch). Definition of the Loosely-synchronous Transfer Mode (LTM) and the Synchronous Protocol Stack (SPS) that add synchronous and isochronous services to any existing protocol stack. Performance evaluation of Isochronets

Space Electrochemical Research and Technology (SERT)

The conference provided a forum to assess critical needs and technologies for the NASA electrochemical energy conversion and storage program. It was aimed at providing guidance to NASA on the appropriate direction and emphasis of that program. A series of related overviews were presented in the areas of NASA advanced mission models (space stations, low and geosynchronous Earth orbit missions, planetary missions, and space transportation). Papers were presented and workshops conducted in a variety of technical areas, including advanced rechargeables, advanced concepts, critical physical electrochemical issues, and modeling

Space Power

Appropriate directions for the applied research and technology programs that will develop space power systems for U.S. future space missions beyond 1995 are explored. Spacecraft power supplies; space stations, space power reactors, solar arrays, thermoelectric generators, energy storage, and communication satellites are among the topics discussed