Selection of an optimal substructure in the distributed arithmetic FIR digital filter

Nerekurzivna digitalna sita v porazdeljeni aritmetiki in aritmetiki s fiksno decimalno vejico se uporabljajo v hitrih sistemih za digitalno obdelavo podatkov, kjer se zahteva stabilnost odzivov in linearne fazne poteke pri zahtevanem velikem dušenju ali veliki strmini bokov. Med različnimi realizacijskimi oblikami smo primerjali kaskadno, vzporedno in kombinirano realizacijsko obliko. Primerjali smo frekvenčne lastnosti, kvantizacijski šum in aparaturno kompleksnost.For digital signal processing in high-speed systems FIR digital filters are used, especially in applications where linear time-invariant stable response and linear phase are needed. A fixed point arithmetic is applied in such systems. The hardware main problem in the design of high-speed FIR digital filters is the complexity. In practical realizations of FIR digital filters, the circuits containe many adders, inverters, registers and multipliers. Among these basic digital elements, the multiplier has most of the hardware complexity and its time response is the greatest. A distributed arithmetic was developed for this reason by some authors. In the hardware realization the multiplier is substituted with a memory, adder and register. The partial sum of coefficients is written in the memory. The partial sum from memory with the previous result from the adder divided by two in the adder is calculated. The previous result from the adder is written in the register on b-iteration of the summed partial results is needed for the calculation of one entire product in the case of the distributed arithmetic. b is the number of bits in the input word. The complexity of the hardware realization of all FIR digital filters in the distributed arithmetic is determined with the word length in all substructures, with ripple in passband and stopband and with the width of transition band on the frequency response. With an increase in the word length, sharpness of the frequency response in transition band and reduction of ripple in passband and stopband the number of basic elements and the time response are increased. The capacity of the memory is determined with 2N, N is the number of impulse response coefficients. In modern digital filter designs the sampling frequency is limited to 20MHz and the number of impulse response coefficients to 200. With the new technology of digital circuits this limit will be increased. Our paper deals with the possibility of reducing the memory capacity by using a combined realization form. The combined realization form contains a cascade-connected structure built with a parallel subsection. We present two FIR digital filters in the distributed arithmetic realization form. The first one is realized with digital elements such as logic gates, adders, inverters and registers, and the other one with digital elements and read-write memory. Both forms are suitable for realization in custom-design integrated circuits or in PLD. Another advantage of our contribution is an optimal word length in all subsections with consideration of the roundoff noise and expected ripple in passband and stopband. As a result, an optimal lowpass FIR digital filter in the distributed arithmetic with 61 coefficients of the impulse response usefulness of the combined realization form is presented and analysed. For the combined realization form of the FIR digital filter design impulse response coefficients are needed. These coefficients can be calculated with software such as MATLAB. The impulseresponse coefficients h(k) are the coefficients of transfer function H(z). From the zeros of the transfer function of the FIR digital filter the zeros of the cascade structure are selected. This selection requires approximately an equal number of zeros in all cascaded structures, and a similar frequency response in all cascaded structures with the frequency response of the whole FIR digital filter. With this selection, the hardware complexity of the cascaded structure is almost the same and the magnitude of the output signal from all the cascaded structures is suitably high. The output signal as a response to the input white noise signal is calculated with our program package for simulation of an FIR digital filter structure. Depending on quantization errors, an optimal word length in all sections is chosen. The simulated results and the theoretically calculated quantization errors with linear quantization error models are compared. A simplified method for determination of the optimal word length was searched for by using theoretically calculated quan

Circulant and skew-circulant matrices as new normal-form realization of IIR digital filters

Normal-form fixed-point state-space realization of IIR (infinite-impulse response) filters are known to be free from both overflow oscillations and roundoff limit cycles, provided magnitude truncation arithmetic is used together with two's-complement overflow features. Two normal-form realizations are derived that utilize circulant and skew-circulant matrices as their state transition matrices. The advantage of these realizations is that the A-matrix has only N (rather than N2) distinct elements and is amenable to efficient memory-oriented implementation. The problem of scaling the internal signals in these structures is addressed, and it is shown that an approximate solution can be obtained through a numerical optimization method. Several numerical examples are included

Implementation of the Trigonometric LMS Algorithm using Original Cordic Rotation

The LMS algorithm is one of the most successful adaptive filtering algorithms. It uses the instantaneous value of the square of the error signal as an estimate of the mean-square error (MSE). The LMS algorithm changes (adapts) the filter tap weights so that the error signal is minimized in the mean square sense. In Trigonometric LMS (TLMS) and Hyperbolic LMS (HLMS), two new versions of LMS algorithms, same formulations are performed as in the LMS algorithm with the exception that filter tap weights are now expressed using trigonometric and hyperbolic formulations, in cases for TLMS and HLMS respectively. Hence appears the CORDIC algorithm as it can efficiently perform trigonometric, hyperbolic, linear and logarithmic functions. While hardware-efficient algorithms often exist, the dominance of the software systems has kept those algorithms out of the spotlight. Among these hardware- efficient algorithms, CORDIC is an iterative solution for trigonometric and other transcendental functions. Former researches worked on CORDIC algorithm to observe the convergence behavior of Trigonometric LMS (TLMS) algorithm and obtained a satisfactory result in the context of convergence performance of TLMS algorithm. But revious researches directly used the CORDIC block output in their simulation ignoring the internal step-by-step rotations of the CORDIC processor. This gives rise to a need for verification of the convergence performance of the TLMS algorithm to investigate if it actually performs satisfactorily if implemented with step-by-step CORDIC rotation. This research work has done this job. It focuses on the internal operations of the CORDIC hardware, implements the Trigonometric LMS (TLMS) and Hyperbolic LMS (HLMS) algorithms using actual CORDIC rotations. The obtained simulation results are highly satisfactory and also it shows that convergence behavior of HLMS is much better than TLMS.Comment: 12 pages, 5 figures, 1 table. Published in IJCNC; http://airccse.org/journal/cnc/0710ijcnc08.pdf, http://airccse.org/journal/ijc2010.htm

Pipelined Two-Operand Modular Adders

Pipelined two-operand modular adder (TOMA) is one of basic components used in digital signal processing (DSP) systems that use the residue number system (RNS). Such modular adders are used in binary/residue and residue/binary converters, residue multipliers and scalers as well as within residue processing channels. The design of pipelined TOMAs is usually obtained by inserting an appriopriate number of latch layers inside a nonpipelined TOMA structure. Hence their area is also determined by the number of latches and the delay by the number of latch layers. In this paper we propose a new pipelined TOMA that is based on a new TOMA, that has the smaller area and smaller delay than other known structures. Comparisons are made using data from the very large scale of integration (VLSI) standard cell library

SMT-Based Bounded Model Checking of Fixed-Point Digital Controllers

Digital controllers have several advantages with respect to their flexibility and design's simplicity. However, they are subject to problems that are not faced by analog controllers. In particular, these problems are related to the finite word-length implementation that might lead to overflows, limit cycles, and time constraints in fixed-point processors. This paper proposes a new method to detect design's errors in digital controllers using a state-of-the art bounded model checker based on satisfiability modulo theories. The experiments with digital controllers for a ball and beam plant demonstrate that the proposed method can be very effective in finding errors in digital controllers than other existing approaches based on traditional simulations tools

Nonlinear behaviors of second-order digital filters with two’s complement arithmetic

The main contribution of our work is the further exploration of some novel and counter-intuitive results on nonlinear behaviors of digital filters and provides some analytical analysis for the account of our partial results. The main implications of our results is: (1) one can select initial conditions and design the filter parameters so that chaotic behaviors can be avoided; (2) one can also select the parameters to generate chaos for certain applications, such as chaotic communications, encryption and decryption, fractal coding, etc; (3) we can find out the filter parameters when random-like chaotic patterns exhibited in some local regions on the phase plane by the Shannon entropies

Workshop on Verification and Theorem Proving for Continuous Systems (NetCA Workshop 2005)

Oxford, UK, 26 August 200