327 research outputs found
Self-Learning Hot Data Prediction: Where Echo State Network Meets NAND Flash Memories
Β© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Well understanding the access behavior of hot data is significant for NAND flash memory due to its crucial impact on the efficiency of garbage collection (GC) and wear leveling (WL), which respectively dominate the performance and life span of SSD. Generally, both GC and WL rely greatly on the recognition accuracy of hot data identification (HDI). However, in this paper, the first time we propose a novel concept of hot data prediction (HDP), where the conventional HDI becomes unnecessary. First, we develop a hybrid optimized echo state network (HOESN), where sufficiently unbiased and continuously shrunk output weights are learnt by a sparse regression based on L2 and L1/2 regularization. Second, quantum-behaved particle swarm optimization (QPSO) is employed to compute reservoir parameters (i.e., global scaling factor, reservoir size, scaling coefficient and sparsity degree) for further improving prediction accuracy and reliability. Third, in the test on a chaotic benchmark (Rossler), the HOESN performs better than those of six recent state-of-the-art methods. Finally, simulation results about six typical metrics tested on five real disk workloads and on-chip experiment outcomes verified from an actual SSD prototype indicate that our HOESN-based HDP can reliably promote the access performance and endurance of NAND flash memories.Peer reviewe
Flash Memory Devices
Flash memory devices have represented a breakthrough in storage since their inception in the mid-1980s, and innovation is still ongoing. The peculiarity of such technology is an inherent flexibility in terms of performance and integration density according to the architecture devised for integration. The NOR Flash technology is still the workhorse of many code storage applications in the embedded world, ranging from microcontrollers for automotive environment to IoT smart devices. Their usage is also forecasted to be fundamental in emerging AI edge scenario. On the contrary, when massive data storage is required, NAND Flash memories are necessary to have in a system. You can find NAND Flash in USB sticks, cards, but most of all in Solid-State Drives (SSDs). Since SSDs are extremely demanding in terms of storage capacity, they fueled a new wave of innovation, namely the 3D architecture. Today β3Dβ means that multiple layers of memory cells are manufactured within the same piece of silicon, easily reaching a terabit capacity. So far, Flash architectures have always been based on "floating gate," where the information is stored by injecting electrons in a piece of polysilicon surrounded by oxide. On the contrary, emerging concepts are based on "charge trap" cells. In summary, flash memory devices represent the largest landscape of storage devices, and we expect more advancements in the coming years. This will require a lot of innovation in process technology, materials, circuit design, flash management algorithms, Error Correction Code and, finally, system co-design for new applications such as AI and security enforcement
High-Density Solid-State Memory Devices and Technologies
This Special Issue aims to examine high-density solid-state memory devices and technologies from various standpoints in an attempt to foster their continuous success in the future. Considering that broadening of the range of applications will likely offer different types of solid-state memories their chance in the spotlight, the Special Issue is not focused on a specific storage solution but rather embraces all the most relevant solid-state memory devices and technologies currently on stage. Even the subjects dealt with in this Special Issue are widespread, ranging from process and design issues/innovations to the experimental and theoretical analysis of the operation and from the performance and reliability of memory devices and arrays to the exploitation of solid-state memories to pursue new computing paradigms
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Όλ¬Έ(λ°μ¬) -- μμΈλνκ΅λνμ : 곡과λν μ»΄ν¨ν°κ³΅νλΆ, 2021.8. κΉμ§ν.The development of ultra-large NAND flash storage devices (SSDs) is recently made possible by NAND flash memory semiconductor process scaling and multi-leveling techniques, and NAND package technology, which enables continuous increasing of storage capacity by mounting many NAND flash memory dies in an SSD.
As the capacity of an SSD increases, the total cost of ownership of the storage system can be reduced very effectively, however due to limitations of ultra-large SSDs in reliability and performance,
there exists some obstacles for ultra-large SSDs to be widely adopted.
In order to take advantage of an ultra-large SSD, it is necessary to develop new techniques to improve these reliability and performance issues.
In this dissertation, we propose various optimization techniques to solve the reliability and performance issues of ultra-large SSDs. In order to overcome the optimization limitations of the existing approaches, our techniques were designed based on various characteristic evaluation results of NAND flash devices and field failure characteristics analysis results of real SSDs.
We first propose a low-stress erase technique for the purpose of reducing the characteristic deviation between wordlines (WLs) in a NAND flash block. By reducing the erase stress on weak WLs, it effectively slows down NAND degradation and improves NAND endurance. From the NAND evaluation results, the conditions that can most effectively guard the weak WLs are defined as the gerase mode. In addition, considering the user workload characteristics, we propose a technique to dynamically select the optimal gerase mode that can maximize the lifetime of the SSD.
Secondly, we propose an integrated approach that maximizes the efficiency of copyback operations to improve performance while not compromising data reliability.
Based on characterization using real 3D TLC flash chips, we propose a novel per-block error propagation model under consecutive copyback operations. Our model significantly increases the number of successive copybacks by exploiting the aging characteristics of NAND blocks. Furthermore, we devise a resource-efficient error management scheme that can handle successive copybacks where pages move around multiple blocks with different reliability.
By utilizing proposed copyback operation for internal data movement, SSD performance can be effectively improved without any reliability issues.
Finally, we propose a new recovery scheme, called reparo, for a
RAID storage system with ultra-large SSDs. Unlike the existing RAID recovery schemes, reparo repairs a failed SSD at the NAND die granularity without replacing it with a new SSD, thus avoiding most of the inter-SSD data copies during a RAID recovery step.
When a NAND die of an SSD fails, reparo exploits a multi-core processor of the SSD controller to identify failed LBAs from the failed NAND die and to recover data from the failed LBAs. Furthermore, reparo ensures no negative post-recovery impact on the performance and lifetime of the repaired SSD.
In order to evaluate the effectiveness of the proposed techniques, we implemented them in a storage device prototype, an open NAND flash storage device development environment, and a real SSD environment. And their usefulness was verified using various benchmarks and I/O traces collected the from real-world applications.
The experiment results show that the reliability and performance of the ultra-large SSD can be effectively improved through the proposed techniques.λ°λ체 곡μ μ λ―ΈμΈν, λ€μΉν κΈ°μ μ μν΄μ μ§μμ μΌλ‘ μ©λμ΄ μ¦κ°νκ³ μλ λ¨μ λΈλ νλμ¬ λ©λͺ¨λ¦¬μ νλμ λΈλ νλμ¬ κΈ°λ° μ€ν λ¦¬μ§ μμ€ν
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Όλ¬Έμμλ λΈλ νλμ¬ λΆλ‘λ΄μ νμ΄μ§λ€κ°μ νΉμ±νΈμ°¨λ₯Ό μ€μ΄κΈ° μν΄μ λμ μΈ μκ±° μ€νΈλ μ€ κ²½κ° κΈ°λ²μ μ μνλ€. μ μλ κΈ°λ²μ λΈλ λΈλ‘μ λ΄κ΅¬μ±μ λ리기 μν΄μ νΉμ±μ΄ μ½ν νμ΄μ§λ€μ λν΄μ λ μ μ μκ±° μ€νΈλ μ€κ° μΈκ°ν μ μλλ‘ λΈλ νκ° κ²°κ³Όλ‘ λΆν° μκ±° μ€νΈλ μ€ κ²½κ° λͺ¨λΈμ ꡬμΆνλ€. λν μ¬μ©μ μν¬λ‘λ νΉμ±μ κ³ λ €νμ¬, μκ±° μ€νΈλ μ€ κ²½κ° κΈ°λ²μ ν¨κ³Όκ° μ΅λν λ μ μλ μ΅μ μ κ²½κ° μμ€μ λμ μΌλ‘ νλ¨ν μ μλλ‘ νλ€. μ΄λ₯Ό ν΅ν΄μ λΈλ λΈλ‘μ μ΄νμν€λ μ£Όμ μμΈμΈ μκ±° λμμ ν¨μ¨μ μΌλ‘ μ μ΄ν¨μΌλ‘μ¨ μ μ₯μ₯μΉμ μλͺ
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Όλ¬Έμμλ μ΄κ³ μ©λ SSDμμ λΈλ νλμ¬μ λ€μ΄(die) λΆλμΌλ‘ μΈν λ μ΄λ(redundant array of independent disks, RAID) 리λΉλ μ€λ²ν€λλ₯Ό μ΅μν νκΈ°μν μλ‘μ΄ RAID 볡ꡬ κΈ°λ²μΈ reparoλ₯Ό μ μνλ€.
Reparoλ SSDμ λν κ΅μ²΄μμ΄ SSDμ λΆλ dieμ λν΄μλ§ λ³΅κ΅¬λ₯Ό μνν¨μΌλ‘μ¨ λ³΅κ΅¬ μ€λ²ν€λλ₯Ό μ΅μννλ€.
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λ° κ³΅κ° λΈλ νλμ¬ μ μ₯μ₯μΉ κ°λ°νκ²½, κ·Έλ¦¬κ³ μ€μ₯ SSDνκ²½μ ꡬνλμμΌλ©°,
μ€μ μμ© νλ‘κ·Έλ¨μ λͺ¨μ¬ν λ€μν λ²€νΈλ§ν¬ λ° μ€μ I/O νΈλ μ΄μ€λ€μ μ΄μ©νμ¬ κ·Έ μ μ©μ±μ κ²μ¦νμλ€.
μ€ν κ²°κ³Ό, μ μλ κΈ°λ²λ€μ ν΅ν΄μ μ΄κ³ μ©λ SSDμ μ λ’°μ± λ° μ±λ₯μ ν¨κ³Όμ μΌλ‘ κ°μ ν μ μμμ νμΈνμλ€.I Introduction 1
1.1 Motivation 1
1.2 Dissertation Goals 3
1.3 Contributions 5
1.4 Dissertation Structure 8
II Background 11
2.1 Overview of 3D NAND Flash Memory 11
2.2 Reliability Management in NAND Flash Memory 14
2.3 UL SSD architecture 15
2.4 Related Work 17
2.4.1 NAND endurance optimization by utilizing page characteristics difference 17
2.4.2 Performance optimizations using copyback operation 18
2.4.3 Optimizations for RAID Rebuild 19
2.4.4 Reliability improvement using internal RAID 20
III GuardedErase: Extending SSD Lifetimes by Protecting Weak Wordlines 22
3.1 Reliability Characterization of a 3D NAND Flash Block 22
3.1.1 Large Reliability Variations Among WLs 22
3.1.2 Erase Stress on Flash Reliability 26
3.2 GuardedErase: Design Overview and its Endurance Model 28
3.2.1 Basic Idea 28
3.2.2 Per-WL Low-Stress Erase Mode 31
3.2.3 Per-Block Erase Modes 35
3.3 Design and Implementation of LongFTL 39
3.3.1 Overview 39
3.3.2 Weak WL Detector 40
3.3.3 WAF Monitor 42
3.3.4 GErase Mode Selector 43
3.4 Experimental Results 46
3.4.1 Experimental Settings 46
3.4.2 Lifetime Improvement 47
3.4.3 Performance Overhead 49
3.4.4 Effectiveness of Lowest Erase Relief Ratio 50
IV Improving SSD Performance Using Adaptive Restricted- Copyback Operations 52
4.1 Motivations 52
4.1.1 Data Migration in Modern SSD 52
4.1.2 Need for Block Aging-Aware Copyback 53
4.2 RCPB: Copyback with a Limit 55
4.2.1 Error-Propagation Characteristics 55
4.2.2 RCPB Operation Model 58
4.3 Design and Implementation of rcFTL 59
4.3.1 EPM module 60
4.3.2 Data Migration Mode Selection 64
4.4 Experimental Results 65
4.4.1 Experimental Setup 65
4.4.2 Evaluation Results 66
V Reparo: A Fast RAID Recovery Scheme for Ultra- Large SSDs 70
5.1 SSD Failures: Causes and Characteristics 70
5.1.1 SSD Failure Types 70
5.1.2 SSD Failure Characteristics 72
5.2 Impact of UL SSDs on RAID Reliability 74
5.3 RAID Recovery using Reparo 77
5.3.1 Overview of Reparo 77
5.4 Cooperative Die Recovery 82
5.4.1 Identifier: Parallel Search of Failed LBAs 82
5.4.2 Handler: Per-Core Space Utilization Adjustment 83
5.5 Identifier Acceleration Using P2L Mapping Information 89
5.5.1 Page-level P2L Entrustment to Neighboring Die 90
5.5.2 Block-level P2L Entrustment to Neighboring Die 92
5.5.3 Additional Considerations for P2L Entrustment 94
5.6 Experimental Results 95
5.6.1 Experimental Settings 95
5.6.2 Experimental Results 97
VI Conclusions 109
6.1 Summary 109
6.2 Future Work 111
6.2.1 Optimization with Accurate WAF Prediction 111
6.2.2 Maximizing Copyback Threshold 111
6.2.3 Pre-failure Detection 112λ°
Reconfigurable three-terminal logic devices using phase-change materials
Conventional solid-state and mass storage memories (such as SRAM, DRAM and the hard disk drive HDD) are facing many technological challenges to meet the ever-increasing demand for fast, low power and cheap data storage solutions. This is compounded by the current conventional computer architectures (such as the von Neumann architecture) with separate processing and storage functionalities and hence data transfer bottlenecks and increased silicon footprint. Beyond the von Neumann computer architecture, the combination of arithmetic-logic processing and (collocally) storage circuits provide a new and promising alternative for computer systems that overcome the many limitations of current technology. However, there are many technical challenges that face the implementation of universal blocks of both logic and memory functions using conventional silicon technology (transistor-transistor logic - TTL, and complementary metal oxide semiconductors - CMOS). Phase-change materials, such as Ge2Sb2Te5 (GST), provide a potential complement or replacement to these technologies to provide both processing and, collocally, storage capability. Existing research in phase-change memory technologies focused on two-terminal non-volatile devices for different memory and logic applications due to their ability to achieve logic-resistive switching in nanosecond time scale, their scalability down to few nanometer-scale cells, and low power requirements. To perform logic functionality, current two-terminal phase-change logic devices need to be connected in series or parallel circuits, and require sequential inputs to perform the required logic function (such as NAND and NOR). In this research programme, three-terminal (3T) non-volatile phase-change memories are proposed and investigated as potential alternative logic cells with simultaneous inputs as reconfigurable, non-volatile logic devices. A vertical 3T logic device structure is proposed in this work based on existing phase-change based memory cell architecture and original concept work by Ovshinsky. A comprehensive, multi-physics finite-element model of the vertical 3T device was constructed in Comsol Multiphysics. This model solves Laplace's equation for the electric potential due to the application of voltage sources. The calculated electric potential and fields provide the Joule heating source in the device, which is used to compute the temperature distribution through solution of the heat diffusion equation, which is necessary to activate the thermally-driven phase transition process. The physically realistic and computationally efficient nucleation- growth model was numerically implemented to model the phase change and resistance change in the Ge2Sb2Te5 (GST) phase-change material in the device, which is combined with the finite- element model using the Matlab programming interface. The changes in electrical and thermal conductivities in the GST region are taken into account following the thermally activated phase transformations between the amorphous-crystalline states using effective medium theory. To determine the appropriate voltage and temperature conditions for the SET and RESET operations, and to optimise the materials and thicknesses of the thermal and heating layers in the device, comprehensive steady-state parametric simulations were carried out using the finite-element multi-physics model. Simulations of transient cycles of writing (SET) and erasing (RESET) processes using appropriate voltage pulses were then carried out on the designed vertical 3T device to study the phase transformations for practical reconfigurable logic operations. The simulations indicated excellent resistance contrast between the logic 1 and 0 states, and successfully demonstrated the feasibility of programming the logic functions of NAND and NOR gates using this 3T configuration
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