FeFET-based MirrorBit cell for High-density NVM storage

HfO2-based Ferroelectric field-effect transistor (FeFET) has become a center of attraction for non-volatile memory applications because of their low power, fast switching speed, high scalability, and CMOS compatibility. In this work, we show an n-channel FeFET-based Multibit memory, termed MirrorBit, which effectively doubles the chip density via programming the gradient ferroelectric polarizations in the gate using an appropriate biasing scheme. We have experimentally demonstrated MirrorBit on GlobalFoundries HfO2-based FeFET devices fabricated at 28 nm bulk HKMG CMOS technology. Retention of MirrorBit states has been shown up to $10^5$ s at different temperatures. Also, the endurance is found to be more than $10^3$ cycles. A TCAD simulation is also presented to explain the origin and working of MirrorBit states based on the FeFET model calibrated using the GlobalFoundries FeFET device. We have also proposed the array-level implementation and sensing methodology of the MirrorBit memory. Thus, we have converted 1-bit FeFET into 2-bit FeFET using a particular programming scheme in existing FeFET, without needing any notable fabrication process alteration, to double the chip density for high-density non-volatile memory storage.Comment: 6 pages, 9 figure

Intellectual property strategy : analysis of the flash memory industry

Thesis (S.M.M.O.T.)--Massachusetts Institute of Technology, Sloan School of Management, Management of Technology Program, 2006.Page 150 blank.Includes bibliographical references (o, 120-121).This thesis studies the intellectual property strategy of companies in the flash memory industry, with special emphasis on technology and the development of nitride-based flash, a new and emerging type of memory technology. First, general perspectives and frameworks for licensing of patents and know-how are explored. Then, the participants in the flash memory industry are mapped to a product value chain, which is in turn mapped to an intellectual property value chain. We use a patent database analysis software IPVision in order to examine the patent portfolios of some of the memory chip companies. Analysis of the patent positions allows us to draw conclusions about the direction of technology development.by Tomoko H. Ogura.S.M.M.O.T

I Am Error

I Am Error is a platform study of the Nintendo Family Computer (or Famicom), a videogame console first released in Japan in July 1983 and later exported to the rest of the world as the Nintendo Entertainment System (or NES). The book investigates the underlying computational architecture of the console and its effects on the creative works (e.g. videogames) produced for the platform. I Am Error advances the concept of platform as a shifting configuration of hardware and software that extends even beyond its ‘native’ material construction. The book provides a deep technical understanding of how the platform was programmed and engineered, from code to silicon, including the design decisions that shaped both the expressive capabilities of the machine and the perception of videogames in general. The book also considers the platform beyond the console proper, including cartridges, controllers, peripherals, packaging, marketing, licensing, and play environments. Likewise, it analyzes the NES’s extension and afterlife in emulation and hacking, birthing new genres of creative expression such as ROM hacks and tool-assisted speed runs. I Am Error considers videogames and their platforms to be important objects of cultural expression, alongside cinema, dance, painting, theater and other media. It joins the discussion taking place in similar burgeoning disciplines—code studies, game studies, computational theory—that engage digital media with critical rigor and descriptive depth. But platform studies is not simply a technical discussion—it also keeps a keen eye on the cultural, social, and economic forces that influence videogames. No platform exists in a vacuum: circuits, code, and console alike are shaped by the currents of history, politics, economics, and culture—just as those currents are shaped in kind

Fabrication and characterization of memory devices based on organic/polymer materials

Ph.DDOCTOR OF PHILOSOPH

National Aeronautics and Space Administration (NASA)/American Society for Engineering Education (ASEE) Summer Faculty Fellowship Program, 1993, volume 2

The JSC NASA/ASEE Summer Faculty Fellowship Program was conducted by Texas A&M University and JSC. The objectives of the program, which began nationally in 1964 and at JSC in 1965, are (1) to further the professional knowledge of qualified engineering and science faculty members; (2) to stimulate an exchange of ideas between participants and NASA; (3) to enrich and refresh the research and teaching activities of participant's institutions; and (4) to contribute to the research objectives of the NASA centers. Each faculty fellow spent at least 10 weeks at JSC engaged in a research project in collaboration with a NASA/JSC colleague. A compilation of the final reports on the research projects completed by the faculty fellows during the summer of 1993 is presented

Electrical Characterisation of Ferroelectric Field Effect Transistors based on Ferroelectric HfO2 Thin Films

Ferroelectric field effect transistor (FeFET) memories based on a new type of ferroelectric material (silicon doped hafnium oxide) were studied within the scope of the present work. Utilisation of silicon doped hafnium oxide (Si:HfO2) thin films instead of conventional perovskite ferroelectrics as a functional layer in FeFETs provides compatibility to the CMOS process as well as improved device scalability. The influence of different process parameters on the properties of Si:HfO2 thin films was analysed in order to gain better insight into the occurrence of ferroelectricity in this system. A subsequent examination of the potential of this material as well as its possible limitations with the respect to the application in non-volatile memories followed. The Si:HfO2-based ferroelectric transistors that were fully integrated into the state-of-the-art high-k metal gate CMOS technology were studied in this work for the first time. The memory performance of these devices scaled down to 28 nm gate length was investigated. Special attention was paid to the charge trapping phenomenon shown to significantly affect the device behaviour.:1 Introduction 2 Fundamentals 2.1 Non-volatile semiconductor memories 2.2 Emerging memory concepts 2.3 Ferroelectric memories 3 Characterisation methods 3.1 Memory characterisation tests 3.2 Ferroelectric memory specific characterisation tests 3.3 Trapping characterisation methods 3.4 Microstructural analyses 4 Sample description 4.1 Metal-insulator-metal capacitors 4.2 Ferroelectric field effect transistors 5 Stabilisation of the ferroelectric properties in Si:HfO2 thin films 5.1 Impact of the silicon doping 5.2 Impact of the post-metallisation anneal 5.3 Impact of the film thickness 5.4 Summary 6 Electrical properties of the ferroelectric Si:HfO2 thin films 6.1 Field cycling effect 6.2 Switching kinetics 6.3 Fatigue behaviour 6.4 Summary 7 Ferroelectric field effect transistors based on Si:HfO2 films 7.1 Effect of the silicon doping 7.2 Program and erase operation 7.3 Retention behaviour 7.4 Endurance properties 7.5 Impact of scaling on the device performance 7.6 Summary 8 Trapping effects in Si:HfO2-based FeFETs 8.1 Trapping kinetics of the bulk Si:HfO2 traps 8.2 Detrapping kinetics of the bulk Si:HfO2 traps 8.3 Impact of trapping on the FeFET performance 8.4 Modified approach for erase operation 8.5 Summary 9 Summary and Outloo

Low Energy Ion Beam Synthesis of Si Nanocrystals for Nonvolatile Memories - Modeling and Process Simulations

Metal-Oxide-Silicon Field-Effect-Transistors with a layer of electrically isolated Si nanocrystals (NCs) embedded in the gate oxide are known to improve conventional floating gate flash memories. Data retention, program and erase speeds as well as the memory operation voltages can be substantially improved due to the discrete charge storage in the isolated Si NCs. Using ion beam synthesis, Si NCs can be fabricated along with standard CMOS processing. The optimization of the location and size of ion beam synthesized Si NCs requires a deeper understanding of the mechanisms involved, which determine (i) the built-up of Si supersaturation by high-fluence ion implantation and (ii) NC formation by phase separation. For that aim, process simulations have been conducted that address both aspects on a fundamental level and, on the other hand, are able to avoid tedious experiments. The built-up of a Si supersaturation by high-fluence ion implantation were studied using dynamic binary collision calculations with TRIDYN and have lead to a prediction of Si excess depth profiles in thin gate oxides of a remarkable quality. These simulations include in a natural manner high fluence implantation effects as target erosion by sputtering, target swelling and ion beam mixing. The second stage of ion beam synthesis is modeled with the help of a tailored kinetic Monte Carlo code that combines a detailed kinetic description of phase separation on atomic level with the required degree of abstraction that is necessary to span the timescales involved. Large ensembles of Si NCs were simulated reaching the late stages of NC formation and dissolution at simulation sizes that allowed a direct comparison with experimental studies, e.g. with electron energy loss resolved TEM investigations. These comparisons reveal a nice degree of agreement, e.g. in terms of predicted and observed precipitate morphologies for different ion fluences. However, they also point clearly onto impact of additional external influences as, e.g., the oxidation of implanted Si by absorbed humidity, which was identified with the help of these process simulations. Moreover, these simulations are utilized as a general tool to identify optimum processing regimes for a tailored Si NC formation for NC memories. It is shown that key properties for NC memories as the tunneling distance from the transistor channel to the Si NCs, the NC morphology, size and density can be adjusted accurately despite of the involved degree of self-organization. Furthermore, possible lateral electron tunneling between neighboring Si NCs is evaluated on the basis of the performed kinetic Monte Carlo simulations