Design of Ternary Memory Cell Using QDGFET

Ternary logic is a promising option to conventional binary logic because it can handle higher information in less number of gate count. Less number of gates requires less area in a chip which is equivalent to gold in today’s nano scale circuits. A novel design of a ternary memory cell based on QDGFETs is proposed. Memory cell is made of two back to back connected inverters. It is the conventional 6T memory cell design. Main advantage of QDGFET is that it can be used directly by replacing CMOS in the circuit without making any changes. Embedded memory requires the largest share of area in modern high-performance circuit designs. As the technology progresses the demand for high capacity memories also increases. So to fulfil this demand, researchers are trying to come up with new technology and solutions. The use of ternary logic instead of binary logic is a possible solution. So in this paper I have designed a ternary memory cell which stores one bit of ternary logic data

FLASH MEMORY DEVICES WITH METAL FLOATING GATE/METAL NANOCRYSTALS AS THE CHARGE STORAGE LAYER: A STATUS REVIEW

Traditional flash memory devices consist of Polysilicon Control Gate (CG) – Oxide-Nitride-Oxide (ONO - Interpoly Dielectric) – Polysilicon Floating Gate (FG) – Silicon Oxide (Tunnel dielectric) – Substrate. The dielectrics have to be scaled down considerably in order to meet the escalating demand for lower write/erase voltages and higher density of cells. But as the floating gate dimensions are scaled down the charge stored in the floating gate leak out more easily via thin tunneling oxide below the floating gate which causes serious reliability issues and the whole amount of stored charge carrying information can be lost. The possible route to eliminate this problem is to use high-k based interpoly dielectric and to replace the polysilicon floating gate with a metal floating gate. At larger physical thickness, these materials have similar capacitance value hence avoiding tunneling effect.  Discrete nanocrystal memory has also been proposed to solve this problem. Due to its high operation speed, excellent scalability and higher reliability it has been shown as a promising candidate for future non-volatile memory applications. This review paper focuses on the recent efforts and research activities related to the fabrication and characterization of non-volatile memory device with metal floating gate/metal nanocrystals as the charge storage layer

Process Optimization and Downscaling of a Single Electron Single Dot Memory

This paper presents the process optimization of a single-electron nanoflash electron memory. Self-aligned single dot memory structures have been fabricated using a wet anisotropic oxidation of a silicon nanowire. One of the main issue was to clarify the process conditions for the dot formation. Based on the process modeling, the influence of various parameters (oxidation temperature, nanowire shape) has been investigated. The necessity of a sharp compromise between these different parameters to ensure the presence of the memory dot has been established. In order to propose an aggressive memory cell, the downscaling of the device has been carefully studied. Scaling rules show that the size of the original device could be reduced by a factor of 2. This point has been previously confirmed by the realization of single-electron memory devices

Progress in Nanoporous Templates: Beyond Anodic Aluminum Oxide and Towards Functional Complex Materials

Successful synthesis of ordered porous, multi-component complex materials requires a series of coordinated processes, typically including fabrication of a master template, deposition of materials within the pores to form a negative structure, and a third deposition or etching process to create the final, functional template. Translating the utility and the simplicity of the ordered nanoporous geometry of binary oxide templates to those comprising complex functional oxides used in energy, electronic, and biology applications has been met with numerous critical challenges. This review surveys the current state of commonly used complex material nanoporous template synthesis techniques derived from the base anodic aluminum oxide (AAO) geometry

RESISTIVE SWITCHING CHARACTERISTICS OF NANOSTRUCTURED AND SOLUTION-PROCESSED COMPLEX OXIDE ASSEMBLIES

Miniaturization of conventional nonvolatile (NVM) memory devices is rapidly approaching the physical limitations of the constituent materials. An emerging random access memory (RAM), nanoscale resistive RAM (RRAM), has the potential to replace conventional nonvolatile memory and could foster novel type of computing due to its fast switching speed, high scalability, and low power consumption. RRAM, or memristors, represent a class of two terminal devices comprising an insulating layer, such as a metal oxide, sandwiched between two terminal electrodes that exhibits two or more distinct resistance states that depend on the history of the applied bias. While the sudden resistance reduction into a conductive state in metal oxide insulators has been known for almost 50 years, the fundamental resistive switching mechanism is a complex phenomenon that is still long-debated, complex process. Further improvements to existing memristor performance require a complete understanding of memristive properties under various operation conditions. Additional technical issues also remain, such as the development of facile, low-cost fabrication methods as an alternative to expensive, ultra-high vacuum (UHV) deposition methods. This collection of work explores resistive switching within metal oxide-based memristive material assemblies by analyzing the fundamental physical insulating material properties. Chapter 3 aims to translate the utility and simplicity of the highly ordered anodic aluminum oxide (AAO) template structure to complex, yet more functional (memristive) materials. Functional oxides possessing ordered, scalable nanoporous arrays and nanocapacitor arrays over a large area is of interest to both the fields of next-generation electronics and energy storing/harvesting devices. Here their switching performance will be evaluated using conductive atomic force microscopy (C-AFM). Chapter 4 demonstrates a convective self-assembly fabrication method that effectively enables the synthesis of a low-cost solution processed memristor comprising binary oxide and perovskite ABO3 nanocrystals of varying diameter. Chapter 5 systematically compares the influence of inter-nanoparticle distance on the threshold switching SET voltage of hafnium oxide (HfO2) memristors. Utilizing shorter phosphonic acid ligands with higher binding affinity on the nanocrystal surface enabled a record-low SET voltage to be achieved. Chapter 6 extends the scope to the fine tuning of solution processed memristors with two types of perovskites nanocrystals. The primary advantage of nanocrystal memristors is the ability to draw from additional degrees of freedom by tuning the constituent nanocrystal material properties. Recent advancement of solution phase techniques enables a high degree of controllability over the nanocrystal size and structure. Thus, this work found in this dissertation aims to understand and decouple the effects of the geometric size and substitutional nanocrystal parameters on resistive switching

Nematic Liquid Crystal Composite Materials for DC and RF Switching

Liquid Crystals (LCs) are widely used in display devices, electro-optic modulators, and optical switches. A field-induced electrical conductivity modulation in pure liquid crystals is very low which makes it less preferable for direct current (DC) and radio-frequency (RF) switching applications. According to the literature, a conductivity enhancement is possible by nanoparticle doping. Considering this aspect, we reviewed published works focused on an electric field-induced conductivity modulation in carbon nanotube-doped liquid crystal composites (LC-CNT composites). A two to four order of magnitude switching in electrical conductivity is observed by several groups. Both in-plane and out-of-plane device configurations are used. In plane configurations are preferable for micro-device fabrication. In this review article, we discussed published works reporting the elastic and molecular interaction of a carbon nanotube (CNT) with LC molecules, temperature and CNT concentration effects on electrical conductivity, local heating, and phase transition behavior during switching. Reversibility and switching speed are the two most important performance parameters of a switching device. It was found that dual frequency nematic liquid crystals (DFNLC) show a faster switching with a good reversibility, but the switching ratio is only two order of magnitudes. A better way to ensure reversibility with a large switching magnitude is to use two pairs of in-plane electrodes in a cross configuration. For completeness and comparison purposes, we briefly reviewed other nanoparticle- (i.e., Au and Ag) doped LC composite’s conductivity behavior as well. Finally, based on the reported works reviewed in this article on field induced conductivity modulation, we proposed a novel idea of RF switching by LC composite materials. To support the idea, we simulated an LC composite-based RF device considering a simple analytical model. Our RF analysis suggests that a device made with an LC-CNT composite could show an acceptable performance. Several technological challenges needed to be addressed for a physical realization and are also discussed briefly

Reversible Engineering of Topological Insulator Surface State Conductivity through Optical Excitation

Despite the broadband response, limited optical absorption at a particular wavelength hinders the development of optoelectronics based on Dirac fermions. Heterostructures of graphene and various semiconductors have been explored for this purpose, while non-ideal interfaces often limit the performance. The topological insulator is a natural hybrid system, with the surface states hosting high-mobility Dirac fermions and the small-bandgap semiconducting bulk state strongly absorbing light. In this work, we show a large photocurrent response from a field effect transistor device based on intrinsic topological insulator Sn-Bi1.1Sb0.9Te2S. The photocurrent response is non-volatile and sensitively depends on the initial Fermi energy of the surface state, and it can be erased by controlling the gate voltage. Our observations can be explained with a remote photo-doping mechanism, in which the light excites the defects in the bulk and frees the localized carriers to the surface state. This photodoping modulates the surface state conductivity without compromising the mobility, and it also significantly modify the quantum Hall effect of the surface state. Our work thus illustrates a route to reversibly manipulate the surface states through optical excitation, shedding light into utilizing topological surface states for quantum optoelectronics

Physics based modeling of the charging dynamics in silicon nanocrystal non-volatile flash memory cell

Flash memory devices based on continuous floating gate are rapidly approaching their technological limitations due to excessive gate leakage currents, resulting from reduced tunnel oxide thickness. A new architecture based on Si-Nanocrystal floating gate has shown promise through realization of devices with reduced gate leakage current and lower programming and erase voltages. The dominant transport mechanisms in this device are tunneling of electrons from the (3-D) silicon into the (0-D) nanocrystals and Fowler-Nordheim tunneling of carriers from nanocrystals to the bulk Si. In order to accurately model the charging dynamics of such devices, size based quantum confinement effects should be included. A fully physics based model is developed to describe the current-voltage and current-time characteristics of Si-Nanocrystal Floating Gate flash memory cells. The model includes the size dependent quantum confinement effects and Coulomb blockade effects. The results of the model are compared with various experimental results, such as current-voltage characteristics, program time versus gate voltage and drain voltage characteristics and the agreement in general is good. The model is very flexible, and it can be used to investigate the charging dynamics of any type of nanocrystals embedded in any type of dielectric layers. Additionally, a possible process methodology to achieve control on the size and density of the nanocrystals is proposed