A binary self-organizing map and its FPGA implementation

A binary Self Organizing Map (SOM) has been designed and implemented on a Field Programmable Gate Array (FPGA) chip. A novel learning algorithm which takes binary inputs and maintains tri-state weights is presented. The binary SOM has the capability of recognizing binary input sequences after training. A novel tri-state rule is used in updating the network weights during the training phase. The rule implementation is highly suited to the FPGA architecture, and allows extremely rapid training. This architecture may be used in real-time for fast pattern clustering and classification of the binary features

Novel Color Image Compression Algorithm Based-On Quadtree

This paper presents a novel algorithm having two image processing systems that have the ability to compress the colour image. The proposed systems divides the colour image into RGB components, each component is selected to be divided. The division processes of the component into blocks are based on quad tree method. For each selection, the other two components are divided using the same blocks coordinates of the selected divided component. In the first system, every block has three minimum values and three difference values. While the other system, every block has three minimum values and one average difference. From experiments, it is found that the division according to the G component is the best giving good visual quality of the compressed images with appropriate compression ratios. It is also noticed, the performance of the second system is better than the first one. The obtained compression ratios ofthe second system are between 1.3379 and 5.0495 at threshold value 0.1, and between 2.3476 and 8.9713 at threshold value 0.2

SOM neural network design – a new Simulink library based approach targeting FPGA implementation

The paper presents a method for FPGA implementation of Self-Organizing Map (SOM) artificial neural networks with on-chip learning algorithm. The method aims to build up a specific neural network using generic blocks designed in the MathWorks Simulink environment. The main characteristics of this original solution are: on-chip learning algorithm implementation, high reconfiguration capability and operation under real time constraints. An extended analysis has been carried out on the hardware resources used to implement the whole SOM network, as well as each individual component block