A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications

Clocking is an important aspect of digital VLSI system design. The design of high-performance and low-power clocked storage elements is essential and critical to achieving maximum levels of performance and reliability in modern VLSI systems such as Systems on Chips (SoCs). In this thesis, a pulse-clocked double edge-triggered D-flip-flop (PDET) is proposed. PDET uses a new split-output true single-phase clocked (TSPC) latch and when clocked by a short pulse train acts like a double edge-triggered flip-flop. The P-type version of the new TSPC split-output latch is compared with existing TSPC split-output latches in terms of robustness, area, and power efficiency at high-speeds. It is shown that the new split-output latch is more area-power efficient, and significantly more robust, than the existing split-output CMOS latches. The novel double edge-triggered flip-flop uses only eight transistors with only one N-type transistor being clocked. Compared to other double edge-triggered flip-flops, PDET offers advantages in terms of speed, power, and area. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Period-Power product is reduced by 56%-63% compared to other double edge-triggered flip-flops. Simulations are performed using HSPICE in CMOS 0.5 om technology. This design is suitable for high-speed, low-power CMOS VLSI design applications

High-performance low-power microprocessor circuits

This thesis will discuss two critical components of a digital system -- domino logic styles and flip-flops. In today's microprocessors, both domino logic and flip-flops are essential to high-performance and low-power design. Two new domino logic styles are presented and analyzed, Double Edge Triggered (DET) and Double Data Rate (DDR) Domino. Using a CMOS 0.25μm MOSIS model, HSPICE simulations show that a DET & DDR 8-bit adder has a maximum throughput of l.6Gops (Giga Operations per second) and 2Gops, respectively, while a conventional domino adder has only 1Gops. In addition, this thesis proposes a novel master-slave flip-flop. This flip-flop is compared with other known flip-flop structures. Using a CMOS 0.35μm MOSIS model, the new flip-flop was simulated to have an optimal power-delay product. The proposed flip-flop consumes very low power, while having a very small clock load and data load

Individual flip-flops with gated clocks for low power datapaths

Energy consumption has become one of the important factors in digital systems, because of the requirement to dissipate this energy in high-density circuits and to extend the battery life in portable systems such as devices with wireless communication capabilities. Flip-flops are one of the most energy-consuming components of digital circuits. This paper presents techniques to reduce energy consumption by individually deactivating the clock when flip-flops do not have to change their value. Flip-flop structures are proposed and selection criteria given to obtain minimum energy consumption. The structures have been evaluated using energy models and validated by switch-level simulations. For the applications considered, significant energy reductions are achieved.Peer ReviewedPostprint (published version

Power efficient resilient microarchitectures for PVT variability mitigation

Nowadays, the high power density and the process, voltage, and temperature variations became the most critical issues that limit the performance of the digital integrated circuits because of the continuous scaling of the fabrication technology. Dynamic voltage and frequency scaling technique is used to reduce the power consumption while different time relaxation techniques and error recovery microarchitectures are used to tolerate the process, voltage, and temperature variations. These techniques reduce the throughput by scaling down the frequency or flushing and restarting the errant pipeline. This thesis presents a novel resilient microarchitecture which is called ERSUT-based resilient microarchitecture to tolerate the induced delays generated by the voltage scaling or the process, voltage, and temperature variations. The resilient microarchitecture detects and recovers the induced errors without flushing the pipeline and without scaling down the operating frequency. An ERSUT-based resilient 16 × 16 bit MAC unit, implemented using Global Foundries 65 nm technology and ARM standard cells library, is introduced as a case study with 18.26% area overhead and up to 1.5x speedup. At the typical conditions, the maximum frequency of the conventional MAC unit is about 375 MHz while the resilient MAC unit operates correctly at a frequency up to 565 MHz. In case of variations, the resilient MAC unit tolerates induced delays up to 50% of the clock period while keeping its throughput equal to the conventional MAC unit’s maximum throughput. At 375 MHz, the resilient MAC unit is able to scale down the supply voltage from 1.2 V to 1.0 V saving about 29% of the power consumed by the conventional MAC unit. A double-edge-triggered microarchitecture is also introduced to reduce the power consumption extremely by reducing the frequency of the clock tree to the half while preserving the same maximum throughput. This microarchitecture is applied to different ISCAS’89 benchmark circuits in addition to the 16x16 bit MAC unit and the average power reduction of all these circuits is 63.58% while the average area overhead is 31.02%. All these circuits are designed using Global Foundries 65nm technology and ARM standard cells library. Towards the full automation of the ERSUT-based resilient microarchitecture, an ERSUT-based algorithm is introduced in C++ to accelerate the design process of the ERSUT-based microarchitecture. The developed algorithm reduces the design-time efforts dramatically and allows the ERSUT-based microarchitecture to be adopted by larger industrial designs. Depending on the ERSUT-based algorithm, a validation study about applying the ERSUT-based microarchitecture on the MAC unit and different ISCAS’89 benchmark circuits with different complexity weights is introduced. This study shows that 72% of these circuits tolerates more than 14% of their clock periods and 54.5% of these circuits tolerates more than 20% while 27% of these circuits tolerates more than 30%. Consequently, the validation study proves that the ERSUT-based resilient microarchitecture is a valid applicable solution for different circuits with different complexity weights

Low Power Explicit Pulse Triggered Flip-Flop Design Based On A Pass Transistor

In VLSI system design, power consumption is the ambitious issue for the past respective years. Advanced IC fabrication technology grants the use of nano scaled devices, so the power dissipation becomes major problem in the designing of VLSI chips. In this paper we present, a low-power flip-flop (FF) design featuring an explicit type pulse-triggered structure and a modified true single phase clock latch based on a signal feed-through scheme using pass transistor. The offered design successfully figure out the long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better power performance by consuming low power. The proposed design also significantly reduces delay time, set-up time and hold time. Simulation results based on TMC 180nm CMOS technology reveal that the proposed design features the best power and delay performance in several FF designs under comparison

A Novel Approach For Design Of Pulse Triggered Flip-Flop To Enhance Speed And Power

In VLSI Technology, flip-flops contribute a significant portion of chip area and power consumption to overall system design. Pulse triggered flip-flops (P-FF) have single latch and hence simpler in circuit complexity. Use of Explicit type design for P-FF gives the speed advantage. This paper presents various Pulse triggered Flip-flop (P-FF) designs and various techniques to achieve a better design in terms of power consumption and speed. Introduction of simple pass transistor in latch design can be used to speed up data transition. Dual edge triggering can be adopted as it consumes less power as compared to single edge triggering. Also conditional discharge technique can be used to reduce switching activity. The work is done in tanner tool software. DOI: 10.17762/ijritcc2321-8169.15025