Reverse-Conducting Insulated Gate Bipolar Transistor: A Review of Current Technologies

The Reverse Conducting IGBT has several benefits over a separate IGBT and diode solution and has the potential to become the dominant device within many power electronic applications; including, but not limited to, motor control, resonant converters, and switch mode power supplies. However, the device inherently suffers from many undesirable design trade-offs which have prevented its widespread use. One of the most critical issues is the snapback seen in the forward conduction characteristic which can prevent full turn-on of the device and result in the device becoming unsuitable for parallel operation (required in many high voltage modules). This phenomenon can be suppressed but at the expense of the reverse conduction performance. This paper provides an overview of the technical design challenges presented by the RC-IGBT structure and reviews alternative device concepts which have been proposed in literature. Analysis shows that these alternate concepts either present a trade-off in performance characteristics, an inability to be manufactured, or a requirement for a custom gate drive.EPSRC Doctoral Training Partnership scheme (grant RG75686) UK Innovate Project Number 10287

High Efficiency IGBTs through Novel Three-Dimensional Modelling and New Architectures

New Insulated Gate Bipolar Transistor (IGBT) designs are reliant on simulation tools, such as Sentaurus technology computer-aided design (TCAD) models, which allow for rapid device development that could not be achieved by manufacturing prototypes due to the cost and time associated with fabrication. These simulations are, though, computationally expensive and typically most design engineers develop these TCAD models only in two dimensions. This leads to inaccuracies in the model output since manufactured transistors are inherently three-dimensional (3D). Based upon a commercial IGBT, this thesis begins by outlining the development of a 3D TCAD model using design details provided by the manufacturer. Large variations between the experimental data from the manufactured device and the simulation model lead to the discovery of widespread birds-beaking within the IGBT – an uncontrollable processing defect that the manufacturer was unaware of. This thesis presents a new simulation technique to account for this processing error while minimising computational effort and investigates the consequence of this birds-beak on the reliability of the device. The verified 3D IGBT model was also used to determine an optimum cell design that considered critical 3D effects omitted from previous studies. An extensive literature review for the Reverse-Conducting IGBT (RC-IGBT) is provided. It is shown that despite the benefits of the RC-IGBT, the device suffers from many undesirable design trade-offs that have prevented its widespread use. The RC-IGBT designs that have currently been proposed in literature, either present a trade-off in performance, an inability to be manufactured, or a requirement for a custom gate drive. This thesis presents a new RC-IGBT concept, the ‘Dual Implant SuperJunction (SJ) RC-IGBT’ that addresses these concerns and is manufacturable using current state of the art techniques. The concept and proposed manufacturing method enables, for the first time, a full SuperJunction structure to be achieved in a 1.2kV device. In addition, an investigation into a coordinated switching scheme using both a silicon IGBT and silicon-carbide MOSFET was undertaken, which aimed to improve turn-off losses within the IGBT without sacrificing on-state losses. Thermal modelling of the power devices switching under inductive load was explored as the system was optimised to use a SiC MOSFET in excess of its nominal ratings, reducing the overall system cost.EPSRC Doctoral Training Partnership scheme (grant RG75686

Introducing the hybrid unipolar bipolar field effect transistor : the HUBFET

Modern commercial aircraft are becoming increasingly dependent on electrical power. More and more of the systems traditionally powered by hydraulics or pneumatics are being migrated to run on electricity. One consequence of the move towards electrical power is the increase in the storage capacity of the bat- teries used to supplement the power generation. The increase in battery size increases the maximum stress that a short circuit failure can put on the power distribution system. Although such failures are extremely rare, the fail safe switches in the distribution system must be capable of handling extremely high energy short circuits and turning off the power to protect the electrical systems from damage. Traditionally aircraft have used electromechanical relays in this role. However, they are large, heavy and slow to switch. As the potential power level is increased, the slow switching becomes more of a problem. The solution is a semiconductor switch. An IGBT can handle the high short circuit currents and switches fast enough to prevent short circuits damaging key systems. However, the inherent voltage drop in the forward current path significantly reduces its efficiency during nominal operation. A power MOSFET would be considerably more efficient than an IGBT during nominal operation. However, during high current surges, the ohmic behaviour of the switch leads to extremely high power loss and thermal failure. In this thesis a solution to this problem is presented. A new class of semiconductor device is proposed that has the highly efficient low current performance of the power MOSFET and the high current handling capability of the IGBT. The device has been named the Hybrid Unipolar Bipolar Field Effect Transistor or HUBFET. The HUBFET operates in unipolar mode, like a MOSFET, at low currents and in bipolar mode, like an IGBT, at high currents. The structure of the HUBFET is a merging of the MOSFET and IGBT. It is a vertical device with a traditional MOS gate structure, however the backside consists of alternating regions of both N-type and P-type doping. Through simulation the key on-state characteristics of the HUBFET have been shown. Fabricated test modules have been tested to validate the simulations and to show how the HUBFET can dynamically transistion from unipolar to bipolar mode during a short circuit event. Following the proof of concept the pattern of implants on the backside of the device that give the HUBFET its characteristic were investigated and potential improvements to the design were identified

Development of a fault tolerant MOS field effect power semiconductor switching transistor

This work describes the development of a semiconductor switch to replace an electromechanical contactor as used within the electrical power distribution system of the More Electric Aircraft (MEA; a project begun in the 1990‟s by the United States Air Force). The MEA is safety critical and therefore requires highest reliability components and systems, but subsequent to a short circuit load fault the electro-mechanical contactor switch often welds shut. This risk is increased when using high discharge energy lithium ion dc batteries. Predominately the semiconductor switch controls inductive loads and is required to safely turn off current of up to 10 times the nominal level during sporadic load fault events. The switch requires the lowest static loss (lowest on state resistance), but also the lowest dynamic loss (losses due to the switching event). Presently, unipolar devices provide the lowest dynamic loss, but bipolar devices provide the lowest static loss. One possible solution is use of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the area of which is sized to suit the fault current, but at relatively high cost in terms of silicon area. The resultant area is typically achieved by several die connected in parallel, unfortunately, such a solution suffers from current share imbalance and the potential of cascade die failure. The use of a parallel combination of unipolar and bipolar device types (MOSFET and Insulated Gate Bipolar Transistors, IGBTs) to form a hybrid appears to offer the potential to reduce the silicon area, and static loss, whilst reducing the impact of the increased dynamic losses of the IGBT. Unfortunately, this goal requires optimised gate timing of the resultant hybrid which proves challenging if the load current is to be shared appropriately during fault switching in order to prevent failure. Some form of single MOS (Metal Oxide Semiconductor) gated integrated hybrid device with self biased bipolar injection is therefore required to ensure highest reliability through a non latching design which offers lowest losses under all conditions and achieves an even temperature distribution. In this work the novel concept of the integrated hybrid device has been investigated at a low Blocking Voltage (BV) rating of 100 V, using computer simulation. The three terminal hybrid silicon DMOS (Double diffused Metal Oxide Semiconductor) device utilises a novel merged Schottky p-type injector to provide self biased entry into a reduced static loss bipolar state in the event of high fault current. The device achieves a specific on state resistance, R(ON,SP) = 1.16 mΩcm2 in bipolar mode (with BV=84 V), that is below the silicon limit line and requires half the area of a traditional unipolar MOSFET to conduct fault current. During comparative standard unclamped inductive switching trials, the hybrid device provides a self clamping action which enables increased inductive energy switching (higher inductance and/or higher load current), relative to that achieved by either the MOSFET or IGBT. The hybrid conducting in bipolar mode switches an inductive load off much faster than that typically achieved by an IGBT (toff =20 ns, in comparison to typically >10 μs for an IGBT). This results in a low turn off energy for the hybrid (1.26*10-4 J/cm2) as compared to that of the IGBT (8.72*10-3 J/cm2). The hybrid dynamic performance is enhanced by the action of the merged Schottky contact which, unlike the IGBT, acts to limit the emitter base voltage (VEB) of the internal PNP Bipolar Junction Transistor, BJT (the integral PNP BJT is otherwise a shared feature with the IGBT). The self biased bipolar activation is achieved at a forward bias (VAK) =1.3 V at temperature (T)= 300 K. The device is latch up free across the operational temperature range of T=233 K to 400 K. A viable charge balanced structure to increase the BV rating to approximately 600 V is also proposed. The resulting performance of the single gated, self biased, hybrid, utilising a novel merged Schottky/P type injector, could lead to a new class of rugged MOS gated power switching devices in silicon and potentially silicon carbide

Novel Power Electronic Device Structures for Power Conditioning Applications

The work presented in this thesis contains an investigation into the methods by which the semiconductor device performance can be improved with an aim to reduce the overall losses in the power conversion system. The types of devices discussed and evaluated in this thesis include Silicon MOSFETs, IGBT, CIGBT and GaN HEMT devices. The performance improvement methods suggested in literature usually involve a trade-off of device characteristics with one another. Therefore an investigation into new device technologies and structures is deemed necessary such that the performance trade-off can be avoided or be improved

Conception, fabrication, caractérisation et modélisation de transistors MOSFET haute tension en technologie avancée SOI (Silicon-On-Insulator)

Nowadays the scaling of bulk silicon CMOS technologies is reaching physical limits. In this context, the FDSOI technology (fully depleted silicon-on-insulator) becomes an alternative for the industry because of its superior performances. The use of an ultra-thin SOI substrate provides an improvement of the MOSFETs behaviour and guarantees their electrostatic integrity for devices of 28nm and below. The development of high-voltage applications such DC/DC converters, voltage regulators and power amplifiers become necessary to integrate new functionalities in the technology. However, the standard devices are not designed to handle such high voltages. To overcome this limitation, this work is focused on the design of a high voltage MOSFET in FDSOI. Through simulations and electrical characterizations, we are exploring several solutions such as the hybridization of the SOI substrate (local opening of the buried oxide) or the implementation in the silicon film. An innovative architecture on SOI, the Dual Ground Plane EDMOS, is proposed, characterized and modelled. It relies on the biasing of a dedicated ground plane introduced below the device to offer promising RON.S/BV trade-off for the targeted applications.A l’heure où la miniaturisation des technologies CMOS sur substrat massif atteint des limites, la technologie FDSOI (silicium sur isolant totalement déserté) s’impose comme une alternative pour l’industrie en raison de ses meilleures performances. Dans cette technologie, l’utilisation d’un substrat SOI ultramince améliore le comportement des transistors MOSFETs et garantit leur intégrité électrostatique pour des dimensions en deçà de 28nm. Afin de lui intégrer de nouvelles fonctionnalités, il devient nécessaire de développer des applications dites « haute tension » comme les convertisseurs DC/DC, les régulateurs de tension ou encore les amplificateurs de puissance. Cependant les composants standards de la technologie CMOS ne sont pas capables de fonctionner sous les hautes tensions requises. Pour répondre à cette limitation, ces travaux portent sur le développement et l’étude de transistors MOS haute tension en technologie FDSOI. Plusieurs solutions sont étudiées à l’aide de simulations numériques et de caractérisations électriques : l’hybridation du substrat (gravure localisée de l’oxyde enterré) et la transposition sur le film mince. Une architecture innovante sur SOI, le Dual Gound Plane EDMOS, est alors proposée, caractérisée et modélisée. Cette architecture repose sur la polarisation d’une seconde grille arrière pour offrir un compromis RON.S/BV prometteur pour les applications visées

Thermal characterisation and reliability analysis of power electronic devices in wind and solar energy systems

Power electronic converters (PECs) are used for conditioning the flow of energy between renewable energy applications and grid or stand-alone connected loads. Insulated gate bipolar transistors (IGBTs) are critical components used as switching devices in PECs. IGBTs are multi-layered devices made of different coefficient of thermal expansion (CTE) based materials. In wind and solar energy applications, IGBT’s reliability is highly influenced by the operating conditions such as variable wind speed and solar irradiance. Power losses occur in switching transient of high current/voltage which causes temperature fluctuations among the layers of the IGBTs. This is the main stress mechanism which accelerates deterioration and eventual failures among IGBT layers due to the dissimilar CTEs. Therefore, proper thermal monitoring is essential for accurate estimation of PECs reliability and end lifetime. Several thermal models have been proposed in literature, which are not capable of representing accurate temperature profiles among multichip IGBTs. These models are mostly derived from offline modelling approaches which cannot take operating conditions and control mechanisms of PECs into account and unable to represent actual heat path among each chip. This research offers an accurate and powerful electro thermal and reliability monitoring tool for such devices. Three-dimensional finite element (FE) IGBT models are implemented using COMSOL, by considering complex heat interactions among each layer. Based on the obtained thermal characteristics, electro thermal and thermo mechanical models were developed in SIMULINK to determine the thermal behaviour of each layer and provide total lifetime consumption analysis. The developed models were verified by real-time (RT) experiments using dSPACE environment. New materials, such as silicon carbide (SiC) devices, were found to exhibit approximately 20°C less thermal profile compared to conventional silicon IGBTs. For PECs used within wind energy systems, PECs driving algorithms were derived within the proposed models and by adjusting switching frequency PECs cycling temperatures were reduced by 12°C which led to a significant reduction in thermal stress; approximately 27 MPa. Total life consumption for the proposed method was calculated as 3.26x10-5 which is approximately 1x10-5 less compared to the other both methods. Effects of maximum power tracking algorithms, used in photovoltaic solar systems, on thermal stress were also explored. The converter’s thermal cycling was found approximately 3 °C higher with the IC algorithm. The steady state temperature was 52.7°C for the IC while it was 42.6 °C for P&O. In conclusion, IC algorithm offers more accurate tracking accuracy; however, this is on the expense of harsher thermal stress which has led to approximately 1.4 times of life consumption compared to P&O under specific operating conditions