Stochastic modeling of nonlinear circuits via SPICE-compatible spectral equivalents

This paper presents a systematic approach for the statistical simulation of nonlinear networks with uncertain circuit elements. The proposed technique is based on spectral expansions of the elements' constitutive equations (I-V characteristics) into polynomial chaos series and applies to arbitrary circuit components, both linear and nonlinear. By application of a stochastic Galerkin method, the stochastic problem is cast in terms of an augmented set of deterministic constitutive equations relating the voltage and current spectral coefficients. These new equations are given a circuit interpretation in terms of equivalent models that can be readily implemented in SPICE-type simulators, as such allowing to take full advantage of existing algorithms and available built-in models for complex devices, like diodes and MOSFETs. The pertinent statistical information of the entire nonlinear network is retrieved via a single simulation. This approach is both accurate and efficient with respect to traditional techniques, such as Monte Carlo sampling. Application examples, including the analysis of a diode rectifier, a CMOS logic gate and a low-noise amplifier, validate the methodology and conclude the paper

Impact on signal integrity of interconnect variabilities

In this paper, literature results on the statistical simulation of lossy and dispersive interconnect networks with uncertain physical properties are extended to general nonlinear circuits. The approach is based on the expansion of circuit voltages and currents into polynomial chaos approximations. The derivation of deterministic circuit equivalents for nonlinear components allows to retrieve the unknown expansion coefficients with a single circuit simulation, that can be carried out via standard SPICE-type solvers. These coefficients provide direct statistical information. The methodology allows the inclusion of arbitrary nonlinear elements and is validated via transmission-line networks terminated by diodes and driven by inverter

Statistical Yield Analysis and Design for Nanometer VLSI

Process variability is the pivotal factor impacting the design of high yield integrated circuits and systems in deep sub-micron CMOS technologies. The electrical and physical properties of transistors and interconnects, the building blocks of integrated circuits, are prone to significant variations that directly impact the performance and power consumption of the fabricated devices, severely impacting the manufacturing yield. However, the large number of the transistors on a single chip adds even more challenges for the analysis of the variation effects, a critical task in diagnosing the cause of failure and designing for yield. Reliable and efficient statistical analysis methodologies in various design phases are key to predict the yield before entering such an expensive fabrication process. In this thesis, the impacts of process variations are examined at three different levels: device, circuit, and micro-architecture. The variation models are provided for each level of abstraction, and new methodologies are proposed for efficient statistical analysis and design under variation. At the circuit level, the variability analysis of three crucial sub-blocks of today's system-on-chips, namely, digital circuits, memory cells, and analog blocks, are targeted. The accurate and efficient yield analysis of circuits is recognized as an extremely challenging task within the electronic design automation community. The large scale of the digital circuits, the extremely high yield requirement for memory cells, and the time-consuming analog circuit simulation are major concerns in the development of any statistical analysis technique. In this thesis, several sampling-based methods have been proposed for these three types of circuits to significantly improve the run-time of the traditional Monte Carlo method, without compromising accuracy. The proposed sampling-based yield analysis methods benefit from the very appealing feature of the MC method, that is, the capability to consider any complex circuit model. However, through the use and engineering of advanced variance reduction and sampling methods, ultra-fast yield estimation solutions are provided for different types of VLSI circuits. Such methods include control variate, importance sampling, correlation-controlled Latin Hypercube Sampling, and Quasi Monte Carlo. At the device level, a methodology is proposed which introduces a variation-aware design perspective for designing MOS devices in aggressively scaled geometries. The method introduces a yield measure at the device level which targets the saturation and leakage currents of an MOS transistor. A statistical method is developed to optimize the advanced doping profiles and geometry features of a device for achieving a maximum device-level yield. Finally, a statistical thermal analysis framework is proposed. It accounts for the process and thermal variations simultaneously, at the micro-architectural level. The analyzer is developed, based on the fact that the process variations lead to uncertain leakage power sources, so that the thermal profile, itself, would have a probabilistic nature. Therefore, by a co-process-thermal-leakage analysis, a more reliable full-chip statistical leakage power yield is calculated

Indirect test of M-S circuits using multiple specification band guarding

Testing analog and mixed-signal circuits is a costly task due to the required test time targets and high end technical resources. Indirect testing methods partially address these issues providing an efficient solution using easy to measure CUT information that correlates with circuit performances. In this work, a multiple specification band guarding technique is proposed as a method to achieve a test target of misclassified circuits. The acceptance/rejection test regions are encoded using octrees in the measurement space, where the band guarding factors precisely tune the test decision boundary according to the required test yield targets. The generated octree data structure serves to cluster the forthcoming circuits in the production testing phase by solely relying on indirect measurements. The combined use of octree based encoding and multiple specification band guarding makes the testing procedure fast, efficient and highly tunable. The proposed band guarding methodology has been applied to test a band-pass Butterworth filter under parametric variations. Promising simulation results are reported showing remarkable improvements when the multiple specification band guarding criterion is used.Peer ReviewedPostprint (author's final draft