Optimization of a Feedforward Symbol Timing Estimator Using Two Samples per Symbol for Optical Coherent QPSK Systems

A feedforward symbol timing estimator using only two samples per symbol is proposed and optimized for optical coherent QPSK signal. Simulation results are presented and discussed.Department of Electrical EngineeringDepartment of Electronic and Information Engineerin

Optimization of a feedforward symbol timing estimator using two samples per symbol for optical coherent QPSK systems

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Digital dual-rate burst-mode receiver for 10G and 1G coexistence in optical access networks

A digital dual-rate burst-mode receiver, intended to support 10 and 1 Gb/s coexistence in optical access networks, is proposed and experimentally characterized. The receiver employs a standard DC-coupled photoreceiver followed by a 20 GS/s digitizer and the detection of the packet presence and line-rate is implemented in the digital domain. A polyphase, 2 samples-per-bit digital signal processing algorithm is then used for efficient clock and data recovery of the 10/1.25 Gb/s packets. The receiver performance is characterized in terms of sensitivity and dynamic range under burst-mode operation for 10/1.25 Gb/s intensity modulated data in terms of both the packet error rate (PER) and the payload bit error rate (pBER). The impact of packet preamble lengths of 16, 32, 48, and 64 bits, at 10 Gb/s, on the receiver performance is investigated. We show that there is a trade-off between pBER and PER that is limited by electrical noise and digitizer clipping at low and high received powers, respectively, and that a 16/2-bit preamble at 10/1.25 Gb/s is sufficient to reliably detect packets at both line-rates over a burst-to-burst dynamic range of 14,5dB with a sensitivity of -18.5dBm at 10 Gb/s. (C)2011 Optical Society of Americ

Hardware Architecture of a QAM Receiver for Short-Range Optical Communications

[EN] Short-reach optical fiber communications systems aim to achieve high throughput, in the order of tens of Gbps. The implementation of these high-speed systems requires parallel processing, which makes low-complexity designs of their subsystems a key to the successful large-scale deployment of this technology. Half-Cycle Nyquist Subcarrier Modulation (HC-SCM) was originally suggested for these systems with the goal of using as much bandwidth as possible and, therefore, achieving high communication rates. Recently, Oversampled Subcarrier Modulation (OVS-SCM) was proposed as an alternative more computational efficient than HC-SCM and also with a better spectral efficiency. This paper proposes a hardware-efficient architecture for an OVS-SCM receiver, which takes into account the inherent parallel processing of these systems. This receiver takes 16 samples in parallel from a 5 GSa/s analog-to-digital converter with a 3.2 GHz 3 dB bandwidth. Design solutions for the frame detection block, the mixer, the resampler, the fractional interpolator, the matched filter and the timing estimator are presented. Our results show that, compared to the HC-SCM receiver, this proposal reduces the computational load of the downconverter stages by 90%. FPGA implementation results are given to demonstrate that our proposal can be implemented in state-of-the-art devices.This work was supported in part by MCIN/AEI/10.13039/501100011033 under Grants RTI2018-101658-B100 and PID2021-126514OB-I00, and in part by the European Union through "ERDF Away of making Europe."Valls Coquillat, J.; Torres Carot, V.; Pérez Pascual, MA.; Almenar Terre, V. (2023). Hardware Architecture of a QAM Receiver for Short-Range Optical Communications. Journal of Lightwave Technology. 41(2):451-461. https://doi.org/10.1109/JLT.2022.321735745146141

Non-data aided digital feedforward timing estimators for linear and nonlinear modulations

We propose to develop new non-data aided (NDA) digital feedforward symbol timing estimators for linear and nonlinear modulations, with a view to reducing the sampling rate of the estimators. The proposed estimators rely on the fact that sufficient statistics exist for a signal sampled at the Nyquist rate. We propose an ad hoc extension to the timing estimator based on the log nonlinearity which performs better than existing estimators at this rate when the operating signal-to-noise ratio (SNR) and the excess bandwidth are low. We propose another alternative estimator for operating at the Nyquist rate that has reduced self-noise at high SNR for large rolloff factors. This can be viewed as an extension of the timing estimator based on the square law nonlinearity. For continuous phase modulations (CPM), we propose two novel estimators that can operate at the symbol rate for MSK type signals. Among the class of NDA feedforward timing estimators we are not aware of any other estimator that can function at symbol rate for this type of signals. We also propose several new estimators for the MSK modulation scheme which operate with reduced sampling rate and are robust to carrier frequency offset and phase offset

Synchronization in all-digital QAM receivers

The recent advance in Field Programmable Gate Array (FPGA) technology has been largely embraced by the communication industry, which views this technology as an effective and economical alternative to the design of Application Specific Integrated Circuits (ASICs). The primary reasons for switching to FPGAs are lower development and non-recurring engineering costs, the flexibility to design to a preliminary standard and adapt the design as the standard evolves, as well as the option of performing software updates in the field. A sector with strong interest in FPGAs is the coaxial cable TV/Internet distribution industry. The creation of soft preliminary standards by the standards organization governing the industry has been the main catalyst for the massive adoption of FPGAs by small to medium size companies, which see this technology as an opportunity to compete in this open market. Both the circuit speed and the economy of FPGA technology depend upon using algorithms that map efficiently into its fabric. Often it is prudent to sacrifice performance to improve either clock speed or economy when developing with FPGAs. The purpose of this research is to both revise and devise synchronization algorithms / structures for cable digital receivers that are to be implemented in FPGA. The main communication scheme used by the coaxial cable distribution industry is digital Quadrature Amplitude Modulation (QAM). The problem of synchronizing to the QAM signal in the receiver is not a new topic and several synchronization-related circuits, which were devised with ASICs implementation in mind, can be found in the open literature. Of interest in this thesis is the non-data-aided digital timing synchronizer that was proposed by D'Andrea to recover timing with no knowledge of the transmitted data. Accurate timing estimation was achieved by reshaping the received signal with a prefilter prior to estimating the timing. A problem with D'Andrea's synchronizer is that the prefilter for reshaping the signal is a relatively long Finite Impulse Response (FIR) filter, whose implementation requires a large number of multipliers. This may not have been an issue with ASICs in as much as the number of hardwired multipliers on a chip is not limited as it is in an FPGA chip. One contribution in this research is to propose an alternative to D'Andrea's synchronizer by replacing the long FIR filter with two single-pole Infinite Impulse Response (IIR) filters that are directly placed inside the timing recovery loop. This novel architecture, which drastically reduces the number of multipliers, is well suited for FPGA implementation. Non-data-aided feedforward synchronizers, which use the same prefilter as D'Andrea's synchronizer, have been receiving significant attention in recent years. Detailed performance analysis for these synchronizers can be found in the open literature. These synchronizers have the advantage of using a feedfordward structure rather than a feedback structure, as it is the case in D'Andrea's synchronizer, to estimate the timing. While D'Andrea's synchronizer has an advantage in performance over a non-data-aided feedforward synchronizer, this has not been reported in the literature. In this thesis a second contribution consists of thoroughly analyzing the steady state timing jitter in D'Andrea synchronizer by deriving a closed-form expression for the noise power spectrum and a simple equation to estimate the timing jitter variance. A third contribution is a novel low-complexity and fast acquisition coherent detector for the detection of Quadrature Phase Shift Keying (QPSK) (i.e., 4-QAM) symbols. This detector performs carrier phase synchronization much faster than a conventional coherent detector. The acquisition time is comparable to that of a differential detector. The fast acquisition comes at the expense of phase jitter, and the end result is a 1 dB performance loss over theoretical coherent detection. This detector can be used in place of the differential detector with no economic penalty. Doing so yields a performance advantage of about 2 dB over differential detection

High-performance signal acquisition algorithms for wireless communications receivers

Due to the uncertainties introduced by the propagation channel, and RF and mixed signal circuits imperfections, digital communication receivers require efficient and robust signal acquisition algorithms for timing and carrier recovery, and interfer- ence rejection. The main theme of this work is the development of efficient and robust signal synchronization and interference rejection schemes for narrowband, wideband and ultra wideband communications systems. A series of novel signal acquisition schemes together with their performance analysis and comparisons with existing state-of-the- art results are introduced. The design effort is first focused on narrowband systems, and then on wideband and ultra wideband systems. For single carrier modulated narrowband systems, it is found that conventional timing recovery schemes present low efficiency, e.g., certain feedback timing recov- ery schemes exhibit the so-called hang-up phenomenon, while another class of blind feedforward timing recovery schemes presents large self-noise. Based on a general re- search framework, we propose new anti-hangup algorithms and prefiltering techniques to speed up the feedback timing recovery and reduce the self-noise of feedforward tim- ing estimators, respectively. Orthogonal frequency division multiplexing (OFDM) technique is well suited for wideband wireless systems. However, OFDM receivers require high performance car-rier and timing synchronization. A new coarse synchronization scheme is proposed for efficient carrier frequency offset and timing acquisition. Also, a novel highly accurate decision-directed algorithm is proposed to track and compensate the residual phase and timing errors after the coarse synchronization step. Both theoretical analysis and computer simulations indicate that the proposed algorithms greatly improve the performance of OFDM receivers. The results of an in-depth study show that a narrowband interference (NBI) could cause serious performance loss in multiband OFDMbased ultra-wideband (UWB) sys- tems. A novel NBI mitigation scheme, based on a digital NBI detector and adaptive analog notch filter bank, is proposed to reduce the effects of NBI in UWB systems. Simulation results show that the proposed NBI mitigation scheme improves signifi- cantly the performance of a standard UWB receiver (this improvement manifests as a signal-to-noise ratio (SNR) gain of 9 dB)

New advances in symbol timing synchronization of single-carrier, multi-carrier and space-time multiple-antenna systems

In this dissertation, the problem of symbol timing synchronization for the following three different communication systems is studied: 1) conventional single-carrier transmissions with single antenna in both transmitter and receiver; 2) single-carrier transmissions with multiple antennas at both transmitter and receiver; and 3) orthogonal frequency division multiplexing (OFDM) based IEEE 802.11a wireless local area networks (WLANs). For conventional single-carrier, single-antenna systems, a general feedforward symbol-timing estimation framework is developed based on the conditional maximum likelihood principle. The proposed algorithm is applied to linear modulations and two commonly used continuous phase modulations: MSK and GMSK. The performance of the proposed estimator is analyzed analytically and via simulations. Moreover, using the newly developed general estimation framework, all the previously proposed digital blind feedforward symbol timing estimators employing second-order statistics are cast into a unified framework. The finite sample mean-square error expression for this class of estimators is established and the best estimators are determined. Simulation results are presented to corroborate the analytical results. Moving on to single-carrier, multiple-antenna systems, we present two algorithms. The first algorithm is based on a heuristic argument and it improves the optimum sample selection algorithm by Naguib et al. so that accurate timing estimates can be obtained even if the oversampling ratio is small. The performance of the proposed algorithm is analyzed both analytically and via simulations. The second algorithm is based on the maximum likelihood principle. The data aided (DA) and non-data aided (NDA) ML symbol timing estimators and their cor- responding CCRB and MCRB in MIMO correlated ??at-fading channels are derived. It is shown that the improved algorithm developed based on the heuristic argument is just a special case of the DA ML estimator. Simulation results under different operating conditions are given to assess and compare the performances of the DA and NDA ML estimators with respect to their corresponding CCRBs and MCRBs. In the last part of this dissertation, the ML timing synchronizer for IEEE 802.11a WLANs on frequency-selective fading channels is developed. The proposed algorithm is compared with four of the most representative timing synchronization algorithms, one specically designed for IEEE 802.11a WLANs and three other algorithms designed for general OFDM frame synchronization