Symbol Synchronization for SDR Using a Polyphase Filterbank Based on an FPGA

This paper is devoted to the proposal of a highly efficient symbol synchronization subsystem for Software Defined Radio. The proposed feedback phase-locked loop timing synchronizer is suitable for parallel implementation on an FPGA. The polyphase FIR filter simultaneously performs matched-filtering and arbitrary interpolation between acquired samples. Determination of the proper sampling instant is achieved by selecting a suitable polyphase filterbank using a derived index. This index is determined based on the output either the Zero-Crossing or Gardner Timing Error Detector. The paper will extensively focus on simulation of the proposed synchronization system. On the basis of this simulation, a complete, fully pipelined VHDL description model is created. This model is composed of a fully parallel polyphase filterbank based on distributed arithmetic, timing error detector and interpolation control block. Finally, RTL synthesis on an Altera Cyclone IV FPGA is presented and resource utilization in comparison with a conventional model is analyzed

Online self-repair of FIR filters

Chip-level failure detection has been a target of research for some time, but today's very deep-submicron technology is forcing such research to move beyond detection. Repair, especially self-repair, has become very important for containing the susceptibility of today's chips. This article introduces a self-repair-solution for the digital FIR filter, one of the key blocks used in DSPs

On the Implementation of Efficient Channel Filters for Wideband Receivers by Optimizing Common Subexpression Elimination Methods

No abstract availabl

Guest editorial for the special issue on software-defined radio transceivers and circuits for 5G wireless communications

Yichuang Sun, Baoyong Chi, and Heng Zhang, Guest Editorial for the Special Issue on Software-Defined Radio Transceivers and Circuits for 5G Wireless Communications, published in IEEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 63 (1): 1-3, January 2016, doi: https://doi.org/10.1109/TCSII.2015.2506979.Peer reviewedFinal Accepted Versio

Verification of Magnitude and Phase Responses in Fixed-Point Digital Filters

In the digital signal processing (DSP) area, one of the most important tasks is digital filter design. Currently, this procedure is performed with the aid of computational tools, which generally assume filter coefficients represented with floating-point arithmetic. Nonetheless, during the implementation phase, which is often done in digital signal processors or field programmable gate arrays, the representation of the obtained coefficients can be carried out through integer or fixed-point arithmetic, which often results in unexpected behavior or even unstable filters. The present work addresses this issue and proposes a verification methodology based on the digital-system verifier (DSVerifier), with the goal of checking fixed-point digital filters w.r.t. implementation aspects. In particular, DSVerifier checks whether the number of bits used in coefficient representation will result in a filter with the same features specified during the design phase. Experimental results show that errors regarding frequency response and overflow are likely to be identified with the proposed methodology, which thus improves overall system's reliability

Analysis and application of digital spectral warping in analog and mixed-signal testing

Spectral warping is a digital signal processing transform which shifts the frequencies contained within a signal along the frequency axis. The Fourier transform coefficients of a warped signal correspond to frequency-domain 'samples' of the original signal which are unevenly spaced along the frequency axis. This property allows the technique to be efficiently used for DSP-based analog and mixed-signal testing. The analysis and application of spectral warping for test signal generation, response analysis, filter design, frequency response evaluation, etc. are discussed in this paper along with examples of the software and hardware implementation

Multi-standard programmable baseband modulator for next generation wireless communication

Considerable research has taken place in recent times in the area of parameterization of software defined radio (SDR) architecture. Parameterization decreases the size of the software to be downloaded and also limits the hardware reconfiguration time. The present paper is based on the design and development of a programmable baseband modulator that perform the QPSK modulation schemes and as well as its other three commonly used variants to satisfy the requirement of several established 2G and 3G wireless communication standards. The proposed design has been shown to be capable of operating at a maximum data rate of 77 Mbps on Xilinx Virtex 2-Pro University field programmable gate array (FPGA) board. The pulse shaping root raised cosine (RRC) filter has been implemented using distributed arithmetic (DA) technique in the present work in order to reduce the computational complexity, and to achieve appropriate power reduction and enhanced throughput. The designed multiplier-less programmable 32-tap FIR-based RRC filter has been found to withstand a peak inter-symbol interference (ISI) distortion of -41 dB