Systematic redundant residue number system codes: analytical upper bound and iterative decoding performance over AWGN and Rayleigh channels

The novel family of redundant residue number system (RRNS) codes is studied. RRNS codes constitute maximum–minimum distance block codes, exhibiting identical distance properties to Reed–Solomon codes. Binary to RRNS symbol-mapping methods are proposed, in order to implement both systematic and nonsystematic RRNS codes. Furthermore, the upper-bound performance of systematic RRNS codes is investigated, when maximum-likelihood (ML) soft decoding is invoked. The classic Chase algorithm achieving near-ML soft decoding is introduced for the first time for RRNS codes, in order to decrease the complexity of the ML soft decoding. Furthermore, the modified Chase algorithm is employed to accept soft inputs, as well as to provide soft outputs, assisting in the turbo decoding of RRNS codes by using the soft-input/soft-output Chase algorithm. Index Terms—Redundant residue number system (RRNS), residue number system (RNS), turbo detection

Performance Enhancement of MIMO-OFDM using Redundant Residue Number System

Telecommunication industry requires high capacity networks with high data rates which are achieved through utilization of Multiple-Input-Multiple-Output (MIMO) communication along with Orthogonal Frequency Division Multiplexing (OFDM) system. Still, the communication channel suffers from noise, interference or distortion due to hardware design limitations, and channel environment, and to combat these challenges, and achieve enhanced performance; various error control techniques are implemented to enable the receiver to detect any possible received errors and correct it and thus; for a certain transmitted signal power the system would have lower Bit Error Rate (BER). The provided research focuses on Redundant Residue Number System (RRNS) coding as a Forward Error Correction (FEC) scheme that improves the performance of MIMO-OFDM based wireless communications in comparison with current methods as Low-Density Parity Check (LDPC) coders at the transmitter side or equalizers at receiver side. The Bit Error Rate (BER) performance over the system was measured using MATLAB tool for different simulated channel conditions, including the effect of signal amplitude reduction and multipath delay spreading. Simulation results had shown that RRNS coding scheme provides an enhancement in system performance over conventional error detection and correction coding schemes by utilizing the distinct features of Residue Number System (RNS)

Floating Point Square Root under HUB Format

Unit-Biased (HUB) is an emerging format based on shifting the representation line of the binary numbers by half unit in the last place. The HUB format is specially relevant for computers where rounding to nearest is required because it is performed simply by truncation. From a hardware point of view, the circuits implementing this representation save both area and time since rounding does not involve any carry propagation. Designs to perform the four basic operations have been proposed under HUB format recently. Nevertheless, the square root operation has not been confronted yet. In this paper we present an architecture to carry out the square root operation under HUB format for floating point numbers. The results of this work keep supporting the fact that the HUB representation involves simpler hardware than its conventional counterpart for computers requiring round-to-nearest mode.Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tec

Error codes constructed in residue number systems with non-pairwise-prime moduli

Codes constructed in a Residue Number System (RNS) of moduli m1, m2, ..., mn are non-binary, arithmetic codes whose codewords are vectors where the ith component is mi-valued (1 ≤ i ≤ n). A new class of codes in RNS is described, where redundancy is introduced by removing the constraint that the moduli of the RNS be pairwise prime. The error-detecting and correcting capabilities of such codes are discussed and a simple approach to error detection, localization and correction is presented. Although the codes under consideration are quite inefficient in some respects, it is shown that codes is examined in more detail. Codes in this subclass, besides correcting all single errors, also correct almost all of double errors and localize some errors of higher multiplicity, with less redundancy than required to construct optimal 2-correcting codes in RNS

Tamper-Resistant Arithmetic for Public-Key Cryptography

Cryptographic hardware has found many uses in many ubiquitous and pervasive security devices with a small form factor, e.g. SIM cards, smart cards, electronic security tokens, and soon even RFIDs. With applications in banking, telecommunication, healthcare, e-commerce and entertainment, these devices use cryptography to provide security services like authentication, identification and confidentiality to the user. However, the widespread adoption of these devices into the mass market, and the lack of a physical security perimeter have increased the risk of theft, reverse engineering, and cloning. Despite the use of strong cryptographic algorithms, these devices often succumb to powerful side-channel attacks. These attacks provide a motivated third party with access to the inner workings of the device and therefore the opportunity to circumvent the protection of the cryptographic envelope. Apart from passive side-channel analysis, which has been the subject of intense research for over a decade, active tampering attacks like fault analysis have recently gained increased attention from the academic and industrial research community. In this dissertation we address the question of how to protect cryptographic devices against this kind of attacks. More specifically, we focus our attention on public key algorithms like elliptic curve cryptography and their underlying arithmetic structure. In our research we address challenges such as the cost of implementation, the level of protection, and the error model in an adversarial situation. The approaches that we investigated all apply concepts from coding theory, in particular the theory of cyclic codes. This seems intuitive, since both public key cryptography and cyclic codes share finite field arithmetic as a common foundation. The major contributions of our research are (a) a generalization of cyclic codes that allow embedding of finite fields into redundant rings under a ring homomorphism, (b) a new family of non-linear arithmetic residue codes with very high error detection probability, (c) a set of new low-cost arithmetic primitives for optimal extension field arithmetic based on robust codes, and (d) design techniques for tamper resilient finite state machines

A Blueprint for Precise and Fault-Tolerant Analog Neural Networks

Analog computing has reemerged as a promising avenue for accelerating deep neural networks (DNNs) due to its potential to overcome the energy efficiency and scalability challenges posed by traditional digital architectures. However, achieving high precision and DNN accuracy using such technologies is challenging, as high-precision data converters are costly and impractical. In this paper, we address this challenge by using the residue number system (RNS). RNS allows composing high-precision operations from multiple low-precision operations, thereby eliminating the information loss caused by the limited precision of the data converters. Our study demonstrates that analog accelerators utilizing the RNS-based approach can achieve ${\geq}99\%$ of FP32 accuracy for state-of-the-art DNN inference using data converters with only $6$-bit precision whereas a conventional analog core requires more than $8$-bit precision to achieve the same accuracy in the same DNNs. The reduced precision requirements imply that using RNS can reduce the energy consumption of analog accelerators by several orders of magnitude while maintaining the same throughput and precision. Our study extends this approach to DNN training, where we can efficiently train DNNs using $7$-bit integer arithmetic while achieving accuracy comparable to FP32 precision. Lastly, we present a fault-tolerant dataflow using redundant RNS error-correcting codes to protect the computation against noise and errors inherent within an analog accelerator