Análisis y validación de algoritmos de separación de fuentes sonoras para aplicaciones en entornos industriales

Este documento presenta la evaluación del costo computacional de las operaciones matemáticas básicas de tres algoritmos de separación de fuentes sonoras: FastlCA, adaptativo basado en gradiente natural y adaptativo EASI basado en gradiente relativo. Estos algoritmos fueron seleccionados por su relativa simplicidad y la viabilidad de implementación en hardware de bajo costo en aplicaciones de localización acústica de agentes móviles en entornos industriales

Low-Power Analog Circuits for Sub-Band Speech Processing

The need for efficient electronics has been increasing by the day, as have the constraints on power and size of the devices. Also the increase in use of mobile and wearable electronics has been leading to innovative methods to conserve power and increase functionality. The traditional approach of signal processing heavily relies on the Digital Signal Processing (DSP) hardware to perform most of the tasks, which has lead to power-hungry circuits. Use of analog front-end devices could prove to be efficient, since most of the real-world data is analog and since the DSP could be spared for more application-specific tasks within the system, thereby resulting in more efficient mixed-signal systems.;The focus in this work is to develop an analog front-end for speech-processing applications with inspiration from biology, and trying to mimic human auditory perception techniques. The circuits are designed in 600nm, 350nm and 180nm CMOS processes and are biased in the sub-threshold region to consume low-power. Also, various modules of the system are connected using multiplexing circuits to allow post-fabrication reconfigurability to suit various applications. These circuits are biased using a network of floating-gate transistors which allow reconfigurability and increased bias accuracy. This thesis mainly describes two modules of the analog front-end used for speech processing: derivative circuit and voltage-mode subtractor circuit, which are used for processing spectrally decomposed signals. These circuits could be used for applications like audio analysis or event detection

Speech Processing Front-end in Low-power Hardware

The objective of this work is to develop analog integrated circuits to serve as low-power auditory front-ends in signal processing systems. An analog front-end can be used for feature-extraction to reduce the requirements of the digital back-end, or to detect and call attention to compelling characteristics of a signal while the back-end is in sleep mode. Such a front-end should be advantageous for speech recognition, noise suppression, auditory scene analysis, hearing prostheses, biological modeling, or hardware-based event detection.;This work presents a spectral decomposition system, which consists of a bandpass filter bank with sub-band magnitude detection. The bandpass filter is low-power and each channel can be individually programmed for different quality factors and passband gains. The novel magnitude detector has a 68 decibel dynamic range, excellent tracking capability, and consumes less than a microwatt of power. The system, which was fabricated in a 0.18 micron process, consists of a 16-channel filter bank and a variety of sub-band computational elements

Interfacing of neuromorphic vision, auditory and olfactory sensors with digital neuromorphic circuits

The conventional Von Neumann architecture imposes strict constraints on the development of intelligent adaptive systems. The requirements of substantial computing power to process and analyse complex data make such an approach impractical to be used in implementing smart systems. Neuromorphic engineering has produced promising results in applications such as electronic sensing, networking architectures and complex data processing. This interdisciplinary field takes inspiration from neurobiological architecture and emulates these characteristics using analogue Very Large Scale Integration (VLSI). The unconventional approach of exploiting the non-linear current characteristics of transistors has aided in the development of low-power adaptive systems that can be implemented in intelligent systems. The neuromorphic approach is widely applied in electronic sensing, particularly in vision, auditory, tactile and olfactory sensors. While conventional sensors generate a huge amount of redundant output data, neuromorphic sensors implement the biological concept of spike-based output to generate sparse output data that corresponds to a certain sensing event. The operation principle applied in these sensors supports reduced power consumption with operating efficiency comparable to conventional sensors. Although neuromorphic sensors such as Dynamic Vision Sensor (DVS), Dynamic and Active pixel Vision Sensor (DAVIS) and AEREAR2 are steadily expanding their scope of application in real-world systems, the lack of spike-based data processing algorithms and complex interfacing methods restricts its applications in low-cost standalone autonomous systems. This research addresses the issue of interfacing between neuromorphic sensors and digital neuromorphic circuits. Current interfacing methods of these sensors are dependent on computers for output data processing. This approach restricts the portability of these sensors, limits their application in a standalone system and increases the overall cost of such systems. The proposed methodology simplifies the interfacing of these sensors with digital neuromorphic processors by utilizing AER communication protocols and neuromorphic hardware developed under the Convolution AER Vision Architecture for Real-time (CAVIAR) project. The proposed interface is simulated using a JAVA model that emulates a typical spikebased output of a neuromorphic sensor, in this case an olfactory sensor, and functions that process this data based on supervised learning. The successful implementation of this simulation suggests that the methodology is a practical solution and can be implemented in hardware. The JAVA simulation is compared to a similar model developed in Nengo, a standard large-scale neural simulation tool. The successful completion of this research contributes towards expanding the scope of application of neuromorphic sensors in standalone intelligent systems. The easy interfacing method proposed in this thesis promotes the portability of these sensors by eliminating the dependency on computers for output data processing. The inclusion of neuromorphic Field Programmable Gate Array (FPGA) board allows reconfiguration and deployment of learning algorithms to implement adaptable systems. These low-power systems can be widely applied in biosecurity and environmental monitoring. With this thesis, we suggest directions for future research in neuromorphic standalone systems based on neuromorphic olfaction

Study, Design and Fabrication of an Analogue VLSI Ormia-Ochracea-Inspired Delay Magnification System

This Thesis entails the development of a low-power delay magnification system inspired by the mechanical structure of the ear of the parasitoid fly Ormia Ochracea (O2). The proposed system is suitable as a preprocessing unit for binaural sound localization processors equipped with miniature acoustic sensors. The core of the Thesis involves the study of a delay magnification system based on the O2 sound localization mechanism and the design and testing of a low-power analog integrated circuit based on a proposed, novel delay magnification system inspired by Ormia Ochracea. The study of the delay magnification system based on the O2 sound localization mechanism is divided into two main parts. The first part studies in detail the delay magnification mechanism of the O2 ears. This study sheds light and tries to comprehend what mechanical parameters of the O2 ears are involved in the delay magnification process and how these parameters contribute to the magnification of the delay. The study presents the signal-flow-graph of the O2 system which can be used as a generic delay magnification model for the O2 ears. We also explore the effects of the tuning of the O2 system parameters on the output interaural time difference (ITD). Inspired by the study of the O2 system, in the second part of our study, we modify the O2 system using simpler building blocks and structure which can provide a delay magnification comparable to the original O2 system. We present a new binaural sound localization system suitable for small ITDs which utilizes the new modified O2 system, cochlea filter banks, cross-correlograms and our re-mapping algorithm and show that it can be used to encode very small input delay values that could not be resolved by means of a conventional binaural processor based on the Jeffress’s coincidence detection model. We evaluate the sound localization performance of our new binaural sound localization system for a single sound source and a sound source in the presence of a competing sound source scenario through detailed simulation. The performance of the proposed system is also explored in the presence of filter bandwidth variation and cochlea filter mismatch. After the study of the O2 delay magnification system, we present an analog VLSI chip which morphs the O2 delay magnification system. To determine what topology is the best morphing platform for the O2 system, we present the design and comparative performance of the O2 system when log-domain and gm-C second order weak-inversion filters are employed. The design of the proposed low-power modified O2 system circuit based on translinear loops is detailed. Its performance is evaluated through detailed simulation. Subsequently the Thesis proceeds with the design, fabrication and testing of the new chip based on the modified O2 circuit. The synthesis and testing of the proposed circuit using 0.35μm AMS CMOS process technology parameters is discussed. Detailed measured results confirm the delay magnification ability of the modified O2 circuit and its compliance with theoretical analysis explained earlier in the Thesis. The fabricated system is tuned to operate in the 100Hz to 1kHz frequency range, is able to achieve a delay gain of approximately 3.5 to 9.5 when the input (physical) delay ranges from 0μs to 20μs, and consumes 13.1μW with a 2 V power supply