User microprogrammable processors for high data rate telemetry preprocessing

The use of microprogrammable processors for the preprocessing of high data rate satellite telemetry is investigated. The following topics are discussed along with supporting studies: (1) evaluation of commercial microprogrammable minicomputers for telemetry preprocessing tasks; (2) microinstruction sets for telemetry preprocessing; and (3) the use of multiple minicomputers to achieve high data processing. The simulation of small microprogrammed processors is discussed along with examples of microprogrammed processors

On the diagnostic emulation technique and its use in the AIRLAB

An aid is presented for understanding and judging the relevance of the diagnostic emulation technique to studies of highly reliable, digital computing systems for aircraft. A short review is presented of the need for and the use of the technique as well as an explanation of its principles of operation and implementation. Details that would be needed for operational control or modification of existing versions of the technique are not described

Image data processing system requirements study. Volume 1: Analysis

Digital image processing, image recorders, high-density digital data recorders, and data system element processing for use in an Earth Resources Survey image data processing system are studied. Loading to various ERS systems is also estimated by simulation

Digital avionics design and reliability analyzer

The description and specifications for a digital avionics design and reliability analyzer are given. Its basic function is to provide for the simulation and emulation of the various fault-tolerant digital avionic computer designs that are developed. It has been established that hardware emulation at the gate-level will be utilized. The primary benefit of emulation to reliability analysis is the fact that it provides the capability to model a system at a very detailed level. Emulation allows the direct insertion of faults into the system, rather than waiting for actual hardware failures to occur. This allows for controlled and accelerated testing of system reaction to hardware failures. There is a trade study which leads to the decision to specify a two-machine system, including an emulation computer connected to a general-purpose computer. There is also an evaluation of potential computers to serve as the emulation computer

Design of testbed and emulation tools

The research summarized was concerned with the design of testbed and emulation tools suitable to assist in projecting, with reasonable accuracy, the expected performance of highly concurrent computing systems on large, complete applications. Such testbed and emulation tools are intended for the eventual use of those exploring new concurrent system architectures and organizations, either as users or as designers of such systems. While a range of alternatives was considered, a software based set of hierarchical tools was chosen to provide maximum flexibility, to ease in moving to new computers as technology improves and to take advantage of the inherent reliability and availability of commercially available computing systems

A high speed special purpose processing unit for logic simulation

The growing complexity of integrated circuits has made simulation, through software-based simulators, very time consuming. The declining cost of hardware and a massive amount of computing time required to simulate logic networks have made the use of hardware simulators very attractive;This dissertation describes the architecture of a specialized, highly parallel, and programmable hardware accelerator for logic simulation. It is designed with commercially available chips in a microprogrammed environment. Any future changes can be accommodated by a change in microcode. High speed is achieved by exploiting parallelism, both in the logic network and the hardware of the processing unit. A standard bus is used for communication between the processing unit and the host computer. A thick , nonstandard bus is used for communication of data within the processing unit at a very high speed. By using two buses, intermediate simulation results could be sent to the host computer in parallel with the simulation of devices. Devices are simulated in a pipelined fashion. Reliability is increased by providing error detection and correction capability for memories and buses, and by providing built-in hardware for diagnostics in a computer-aided environment. Evaluation programs of new devices can be loaded in the processing unit through the host computer. Event driven simulation with arbitrary delays and signal values have been used. Devices are divided into various categories to utilize system resources efficiently. Any device, simple or functional, can be simulated

A machine-independent microprogram development system

The aims of this project are twofold. They are firstly, to implement a microprogram development system that allows the programmer to write microcode for any microprogrammable machine, and secondly, to build a microprogrammable machine, incorporating the user friendliness of a simulator, while still providing the 'hands on' experience obtained actual hardware. Microprogram development involves a two stage process. The first step is to describe the target machine, using format descriptions and mnemonic-based template definitions. The second stage involves using the defined mnemonics to write the microcodes for the target machine. This includes an assembly phase to translate the mnemonics into the binary microinstructions. Three main components constitute the microprogrammable machine. The Arithmetic and Logic Unit (ALU) is built using chips from Advanced Micro Devices' Am29ØØ bit-slice family, the action of the Microprogram Control Unit (MCU) is simulated by software running on an IBM Personal Computer, and a section of the IBM PC's main memory acts as the Control Store (CS) for the system. The ALU is built on a prototyping card that plugs into one of the slots on the IBM PC's mother board. A hardware simulator program, that produces the effect of the ALU, has also been developed. A small assembly language has been developed using the system, to test the various functions of the system. A mini-assembler has also been written to facilitate assembly of the above language. A group of honours students at Rhodes University tested the microprogram development system. Their ideas and suggestions have been tabulated in this report and some of them have been used to enhance the system's performance. The concept of allowing 'inline' microinstructions in the macroprogram is also investigated in this report and a method of implementing this is shown

REGTRAN and MICRO, the implementation of two digital system simulators

REGTRAN (REGister TRANsfer), a hardware description language and SYSSIM (SYStems SIMulation), a simulator for the system described by REGTRAN were originally developed by Edward Pett, Jr [33] at the University of Texas at Austin. These two programs are successfully used to simulate many digital systems of complex nature. It is the primary purpose of this paper to describe the implementation of these two programs for KRONOS at Oregon State University. In this process, various problems, due to the differences in the operating systems, were faced. These problems are discussed in detail and the changes that were made are included. REGTRAN and SYSSIM are not capable of simulating micro-instructions or a microprocessor. For this reason, another simulator MICRO is developed. Detailed description of MICRO and its use as a general purpose simulator as well as a microprogram simulator are given in detail. As an example, partial emulation of DEC PDP-8 is shown. Suggestions for the improvement of MICRO, REGTRAN and SYSSIM are mentioned

Specifications and programs for computer software validation

Three software products developed during the study are reported and include: (1) FORTRAN Automatic Code Evaluation System, (2) the Specification Language System, and (3) the Array Index Validation System