Realization of the farad from the dc quantum Hall effect with digitally-assisted impedance bridges

A new traceability chain for the derivation of the farad from dc quantum Hall effect has been implemented at INRIM. Main components of the chain are two new coaxial transformer bridges: a resistance ratio bridge, and a quadrature bridge, both operating at 1541 Hz. The bridges are energized and controlled with a polyphase direct-digital-synthesizer, which permits to achieve both main and auxiliary equilibria in an automated way; the bridges and do not include any variable inductive divider or variable impedance box. The relative uncertainty in the realization of the farad, at the level of 1000 pF, is estimated to be 64E-9. A first verification of the realization is given by a comparison with the maintained national capacitance standard, where an agreement between measurements within their relative combined uncertainty of 420E-9 is obtained.Comment: 15 pages, 11 figures, 3 table

CMOS Signal Synthesizers for Emerging RF-to-Optical Applications

The need for clean and powerful signal generation is ubiquitous, with applications spanning the spectrum from RF to mm-Wave, to into and beyond the terahertz-gap. RF applications including mobile telephony and microprocessors have effectively harnessed mixed-signal integration in CMOS to realize robust on-chip signal sources calibrated against adverse ambient conditions. Combined with low cost and high yield, the CMOS component of hand-held devices costs a few cents per part per million parts. This low cost, and integrated digital processing, make CMOS an attractive option for applications like high-resolution imaging and ranging, and the emerging 5-G communication space. RADAR techniques when expanded to optical frequencies can enable micrometers of resolution for 3D imaging. These applications, however, impose upto 100x more exacting specifications on power and spectral purity at much higher frequencies than conventional RF synthesizers. This generation of applications will present unconventional challenges for transistor technologies - whether it is to squeeze performance in the conventionally used spectrum, already wrung dry, or signal generation and system design in the relatively emptier mm-Wave to sub-mmWave spectrum, much of the latter falling in the ``Terahertz Gap". Indeed, transistor scaling and innovative device physics leading to new transistor topologies have yielded higher cut-off frequencies in CMOS, though still lagging well behind SiGe and III-V semiconductors. To avoid multimodule solutions with functionality partitioned across different technologies, CMOS must be pushed out of its comfort zone, and technology scaling has to have accompanying breakthroughs in design approaches not only at the system but also at the block level. In this thesis, while not targeting a specific application, we seek to formulate the obstacles in synthesizing high frequency, high power and low noise signals in CMOS and construct a coherent design methodology to address them. Based on this, three novel prototypes to overcome the limiting factors in each case are presented. The first half of this thesis deals with high frequency signal synthesis and power generation in CMOS. Outside the range of frequencies where the transistor has gain, frequency generation necessitates harmonic extraction either as harmonic oscillators or as frequency multipliers. We augment the traditional maximum oscillation frequency metric (fmax), which only accounts for transistor losses, with passive component loss to derive an effective fmax metric. We then present a methodology for building oscillators at this fmax, the Maximum Gain Ring Oscillator. Next, we explore generating large signals beyond fmax through harmonic extraction in multipliers. Applying concepts of waveform shaping, we demonstrate a Power Mixer that engineers transistor nonlinearity by manipulating the amplitudes and relative phase shifts of different device nodes to maximize performance at a specific harmonic beyond device cut-off. The second half proposes a new architecture for an ultra-low noise phase-locked loop (PLL), the Reference-Sampling PLL. In conventional PLLs, a noisy buffer converts the slow, low-noise sine-wave reference signal to a jittery square-wave clock against which the phase of a noisy voltage-controlled oscillator (VCO) is corrected. We eliminate this reference buffer, and measure phase error by sampling the reference sine-wave with the 50x faster VCO waveform already available on chip, and selecting the relevant sample with voltage proportional to phase error. By avoiding the N-squared multiplication of the high-power reference buffer noise, and directly using voltage-mode phase error to control the VCO, we eliminate several noisy components in the controlling loop for ultra-low integrated jitter for a given power consumption. Further, isolation of the VCO tank from any varying load, unlike other contemporary divider-less PLL architectures, results in an architecture with record performance in the low-noise and low-spur space. We conclude with work that brings together concepts developed for clean, high-power signal generation towards a hybrid CMOS-Optical approach to Frequency-Modulated Continuous-Wave (FMCW) Light-Detection-And-Ranging (LIDAR). Cost-effective tunable lasers are temperature-sensitive and have nonlinear tuning profiles, rendering precise frequency modulations or 'chirps' untenable. Locking them to an electronic reference through an electro-optic PLL, and electronically calibrating the control signal for nonlinearity and ambient sensitivity, can make such chirps possible. Approaches that build on the body of advances in electrical PLLs to control the performance, and ease the specification on the design of optical systems are proposed. Eventually, we seek to leverage the twin advantages of silicon-intensive integration and low-cost high-yield towards developing a single-chip solution that uses on-chip signal processing and phased arrays to generate precise and robust chirps for an electronically-steerable fine LIDAR beam

A Low Total Harmonic Distortion Sinusoidal Oscillator Based on Digital Harmonic Cancellation Technique

Sinusoidal oscillator is intensively used in many applications, such as built-in-self-testing and ADC characterization. An innovative medical application for skin cancer detection employed a technology named bio-impedance spectroscopy, which also requires highly linear sinusoidal-wave as the reference clock. Moreover, the generated sinusoidal signals should be tunable within the frequency range from 10kHz to 10MHz, and quadrature outputs are demanded for coherent demodulation within the system. A design methodology of sinusoidal oscillator named digital-harmonic-cancellation (DHC) technique is presented. DHC technique is realized by summing up a set of square-wave signals with different phase shifts and different summing coefficient to cancel unwanted harmonics. With a general survey of literature, some sinusoidal oscillators based on DHC technique are reviewed and categorized. Also, the mathematical algorithm behind the technique is explained, and non-ideality effect is analyzed based on mathematical calculation. The prototype is fabricated in OnSemi 0.5um CMOS technology. The experimental results of this work show that it can achieve HD2 is -59.74dB and HD3 is -60dB at 0.9MHz, and the frequency is tunable over 0.1MHz to 0.9MHz. The chip consumes area of 0.76mm2, and power consumption at 0.9MHz is 2.98mW. Another design in IBM 0.18um technology is still in the phase of design. The preliminary simulation results show that the 0.18um design can realize total harmonic distortion of -72dB at 10MHz with the power consumption of 0.4mW. The new design is very competitive with state-of-art, which will be finished with layout, submitted for fabrication and measured later

Measurements, Models, Systems and Design

531 s.

A Low Total Harmonic Distortion Sinusoidal Oscillator Based on Digital Harmonic Cancellation Technique

Sinusoidal oscillator is intensively used in many applications, such as built-in-self-testing and ADC characterization. An innovative medical application for skin cancer detection employed a technology named bio-impedance spectroscopy, which also requires highly linear sinusoidal-wave as the reference clock. Moreover, the generated sinusoidal signals should be tunable within the frequency range from 10kHz to 10MHz, and quadrature outputs are demanded for coherent demodulation within the system. A design methodology of sinusoidal oscillator named digital-harmonic-cancellation (DHC) technique is presented. DHC technique is realized by summing up a set of square-wave signals with different phase shifts and different summing coefficient to cancel unwanted harmonics. With a general survey of literature, some sinusoidal oscillators based on DHC technique are reviewed and categorized. Also, the mathematical algorithm behind the technique is explained, and non-ideality effect is analyzed based on mathematical calculation. The prototype is fabricated in OnSemi 0.5um CMOS technology. The experimental results of this work show that it can achieve HD2 is -59.74dB and HD3 is -60dB at 0.9MHz, and the frequency is tunable over 0.1MHz to 0.9MHz. The chip consumes area of 0.76mm2, and power consumption at 0.9MHz is 2.98mW. Another design in IBM 0.18um technology is still in the phase of design. The preliminary simulation results show that the 0.18um design can realize total harmonic distortion of -72dB at 10MHz with the power consumption of 0.4mW. The new design is very competitive with state-of-art, which will be finished with layout, submitted for fabrication and measured later

Transceiver architectures and sub-mW fast frequency-hopping synthesizers for ultra-low power WSNs

Wireless sensor networks (WSN) have the potential to become the third wireless revolution after wireless voice networks in the 80s and wireless data networks in the late 90s. This revolution will finally connect together the physical world of the human and the virtual world of the electronic devices. Though in the recent years large progress in power consumption reduction has been made in the wireless arena in order to increase the battery life, this is still not enough to achieve a wide adoption of this technology. Indeed, while nowadays consumers are used to charge batteries in laptops, mobile phones and other high-tech products, this operation becomes infeasible when scaled up to large industrial, enterprise or home networks composed of thousands of wireless nodes. Wireless sensor networks come as a new way to connect electronic equipments reducing, in this way, the costs associated with the installation and maintenance of large wired networks. To accomplish this task, it is necessary to reduce the energy consumption of the wireless node to a point where energy harvesting becomes feasible and the node energy autonomy exceeds the life time of the wireless node itself. This thesis focuses on the radio design, which is the backbone of any wireless node. A common approach to radio design for WSNs is to start from a very simple radio (like an RFID) adding more functionalities up to the point in which the power budget is reached. In this way, the robustness of the wireless link is traded off for power reducing the range of applications that can draw benefit form a WSN. In this thesis, we propose a novel approach to the radio design for WSNs. We started from a proven architecture like Bluetooth, and progressively we removed all the functionalities that are not required for WSNs. The robustness of the wireless link is guaranteed by using a fast frequency hopping spread spectrum technique while the power budget is achieved by optimizing the radio architecture and the frequency hopping synthesizer Two different radio architectures and a novel fast frequency hopping synthesizer are proposed that cover the large space of applications for WSNs. The two architectures make use of the peculiarities of each scenario and, together with a novel fast frequency hopping synthesizer, proved that spread spectrum techniques can be used also in severely power constrained scenarios like WSNs. This solution opens a new window toward a radio design, which ultimately trades off flexibility, rather than robustness, for power consumption. In this way, we broadened the range of applications for WSNs to areas in which security and reliability of the communication link are mandatory

Development of an autonomous lab-on-a-chip system with ion separation and conductivity detection for river water quality monitoring

This thesis discusses the development of a lab on a chip (LOC) ion separation for river water quality monitoring using a capacitively coupled conductivity detector (C⁴D) with a novel baseline suppression technique.Our first interest was to be able to integrate such a detector in a LOC. Different designs (On-capillary design and on-chip design) have been evaluated for their feasibility and their performances. The most suitable design integrated the electrode close to the channel for an enhanced coupling while having the measurement electronics as close as possible to reduce noise. The final chip design used copper tracks from a printed circuit board (PCB) as electrodes, covered by a thin Polydimethylsiloxane (PDMS) layer to act as electrical insulation. The layer containing the channel was made using casting and bonded to the PCB using oxygen plasma. Flow experiments have been conduced to test this design as a detection cell for capacitively coupled contactless conductivity detection (C⁴D).The baseline signal from the system was reduced using a novel baseline suppression technique. Decrease in the background signal increased the dynamic range of the concentration to be measured before saturation occurs. The sensitivity of the detection system was also improved when using the baseline suppression technique. Use of high excitation voltages has proven to increase the sensitivity leading to an estimated limit of detection of 0.0715 μM for NaCl (0.0041 mg/L).The project also required the production of an autonomous system capable of operating for an extensive period of time without human intervention. Designing such a system involved the investigation of faults which can occur in autonomous system for the in-situ monitoring of water quality. Identification of possible faults (Bubble, pump failure, etc.) and detection methods have been investigated. In-depth details are given on the software and hardware architecture constituting this autonomous system and its controlling software

Integrated Circuits and Systems for Smart Sensory Applications

Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in same cases even self-powered, smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power management strategies, low-range wireless communications, integration with sensing devices. In this Special Issue recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications in the following five emerging topics: (I) dedicated short-range communications transceivers; (II) digital smart sensors, (III) implantable neural interfaces, (IV) Power Management Strategies in wireless sensor nodes and (V) neuromorphic hardware