Effect of Clock and Power Gating on Power Distribution Network Noise in 2D and 3D Integrated Circuits

In this work, power supply noise contribution, at a particular node on the power grid, from clock/power gated blocks is maximized at particular time and the synthetic gating patterns of the blocks that result in the maximum noise is obtained for the interval 0 to target time. We utilize wavelet based analysis as wavelets are a natural way of characterizing the time-frequency behavior of the power grid. The gating patterns for the blocks and the maximum supply noise at the Point of Interest at the specified target time obtained via a Linear Programming (LP) formulation (clock gating) and Genetic Algorithm based problem formulation (Power Gating)

An On-chip PVT Resilient Short Time Measurement Technique

As the CMOS technology nodes continue to shrink, the challenges of developing manufacturing tests for integrated circuits become more difficult to address. To detect parametric faults of new generation of integrated circuits such as 3D ICs, on-chip short-time intervals have to be accurately measured. The accuracy of an on-chip time measurement module is heavily affected by Process, supply Voltage, and Temperature (PVT) variations. This work presents a new on-chip time measurement scheme where the undesired effects of PVT variations are attenuated significantly. To overcome the effects of PVT variations on short-time measurement, phase locking methodology is utilized to implement a robust Vernier delay line. A prototype Time-to-Digital Converter (TDC) has been fabricated using TSMC 0.180 µm CMOS technology and experimental measurements have been carried out to verify the performance parameters of the TDC. The measurement results indicate that the proposed solution reduces the effects of PVT variations by more than tenfold compared to a conventional on-chip TDC. A coarse-fine time interval measurement scheme which is resilient to the PVT variations is also proposed. In this approach, two Delay Locked Loops (DLLs) are utilized to minimize the effects of PVT on the measured time intervals. The proposed scheme has been implemented using CMOS 65nm technology. Simulation results using Advanced Design System (ADS) indicate that the measurement resolution varies by less than 0.1ps with ±15% variations of the supply voltage. The proposed method also presents a robust performance against process and temperature variations. The measurement accuracy changes by a maximum of 0.05ps from slow to fast corners. The implemented TDC presents a robust performance against temperature variations too and its measurement accuracy varies a few femto-seconds from -40 ºC to +100 ºC. The principle of robust short-time measurement was used in practice to design and implement a state-of-the-art Coordinate Measuring Machine (CMM) for an industry partner to measure geometrical features of transmission parts with micrometer resolution. The solution developed for the industry partner has resulted in a patent and a product in the market. The on-chip short-time measurement technology has also been utilized to develop a solution to detect Hardware Trojans

3D Signal Strength Mapping of 2.4GHz WiFi Networks

Many commercial businesses operate out of multi-story office buildings. These companies often use many Wi-Fi access points to set up their own wireless network. IT personnel determine proper Wi-Fi access point placement using Wi-Fi strength maps. Conventional Wi-Fi strength maps only provide a two-dimensional view representing the wireless access point\u27s effective range. The signal quality and strength measurements do not include changing vertical elevation. Efficient network layout in a multi-story building requires a system calculating signal quality metrics in three dimensions. This project involves designing and prototyping a system to achieve 2.4GHz Wi-Fi signal quality measurements in a three-dimensional reference plane. The instrument continuously monitors its location and the 2.4GHz Wi-Fi network’s received signal strength. The user generates a 3D model of the 2.4GHz Wi-Fi network coverage using the collected signal metrics

Synthetic Nanoelectronic Probes for Biological Cells and Tissues

Research at the interface between nanoscience and biology could yield breakthroughs in fundamental science and lead to revolutionary technologies. In this review, we focus on the interfaces between nanoelectronics and biology. First, we discuss nanoscale field effect transistors (nanoFETs) as probes to study cellular systems; specifically, we describe the development of nanoFETs that are comparable in size to biological nanostructures involved in communication through synthesized nanowires. Second, we review current progress in multiplexed extracellular sensing using planar nanoFET arrays. Third, we describe the designs and implementation of three distinct nanoFETs used to perform the first intracellular electrical recording from single cells. Fourth, we present recent progress in merging electronic and biological systems at the three-dimensional tissue level by use of macro-porous nanoelectronic scaffolds. Finally, we discuss future developments in this research area, unique challenges and opportunities, and the tremendous impact these nanoFET-based technologies might have on biological and medical sciences.Chemistry and Chemical BiologyEngineering and Applied Science

The Boston University Photonics Center annual report 2015-2016

This repository item contains an annual report that summarizes activities of the Boston University Photonics Center in the 2015-2016 academic year. The report provides quantitative and descriptive information regarding photonics programs in education, interdisciplinary research, business innovation, and technology development. The Boston University Photonics Center (BUPC) is an interdisciplinary hub for education, research, scholarship, innovation, and technology development associated with practical uses of light.This has been a good year for the Photonics Center. In the following pages, you will see that this year the Center’s faculty received prodigious honors and awards, generated more than 100 notable scholarly publications in the leading journals in our field, and attracted $18.9M in new research grants/contracts. Faculty and staff also expanded their efforts in education and training, and cooperated in supporting National Science Foundation sponsored Sites for Research Experiences for Undergraduates and for Research Experiences for Teachers. As a community, we emphasized the theme of “Frontiers in Plasmonics as Enabling Science in Photonics and Beyond” at our annual symposium, hosted by Bjoern Reinhard. We continued to support the National Photonics Initiative, and contributed as a cooperating site in the American Institute for Manufacturing Integrated Photonics (AIM Photonics) which began this year as a new photonics-themed node in the National Network of Manufacturing Institutes. Highlights of our research achievements for the year include an ambitious new DoD-sponsored grant for Development of Less Toxic Treatment Strategies for Metastatic and Drug Resistant Breast Cancer Using Noninvasive Optical Monitoring led by Professor Darren Roblyer, continued support of our NIH-sponsored, Center for Innovation in Point of Care Technologies for the Future of Cancer Care led by Professor Cathy Klapperich, and an exciting confluence of new grant awards in the area of Neurophotonics led by Professors Christopher Gabel, Timothy Gardner, Xue Han, Jerome Mertz, Siddharth Ramachandran, Jason Ritt, and John White. Neurophotonics is fast becoming a leading area of strength of the Photonics Center. The Industry/University Collaborative Research Center, which has become the centerpiece of our translational biophotonics program, continues to focus onadvancing the health care and medical device industries, and has entered its sixth year of operation with a strong record of achievement and with the support of an enthusiastic industrial membership base

Design for pre-bond testability in 3D integrated circuits

In this dissertation we propose several DFT techniques specific to 3D stacked IC systems. The goal has explicitly been to create techniques that integrate easily with existing IC test systems. Specifically, this means utilizing scan- and wrapper-based techniques, two foundations of the digital IC test industry. First, we describe a general test architecture for 3D ICs. In this architecture, each tier of a 3D design is wrapped in test control logic that both manages tier test pre-bond and integrates the tier into the large test architecture post-bond. We describe a new kind of boundary scan to provide the necessary test control and observation of the partial circuits, and we propose a new design methodology for test hardcore that ensures both pre-bond functionality and post-bond optimality. We present the application of these techniques to the 3D-MAPS test vehicle, which has proven their effectiveness. Second, we extend these DFT techniques to circuit-partitioned designs. We find that boundary scan design is generally sufficient, but that some 3D designs require special DFT treatment. Most importantly, we demonstrate that the functional partitioning inherent in 3D design can potentially decrease the total test cost of verifying a circuit. Third, we present a new CAD algorithm for designing 3D test wrappers. This algorithm co-designs the pre-bond and post-bond wrappers to simultaneously minimize test time and routing cost. On average, our algorithm utilizes over 90% of the wires in both the pre-bond and post-bond wrappers. Finally, we look at the 3D vias themselves to develop a low-cost, high-volume pre-bond test methodology appropriate for production-level test. We describe the shorting probes methodology, wherein large test probes are used to contact multiple small 3D vias. This technique is an all-digital test method that integrates seamlessly into existing test flows. Our experimental results demonstrate two key facts: neither the large capacitance of the probe tips nor the process variation in the 3D vias and the probe tips significantly hinders the testability of the circuits. Taken together, this body of work defines a complete test methodology for testing 3D ICs pre-bond, eliminating one of the key hurdles to the commercialization of 3D technology.PhDCommittee Chair: Lee, Hsien-Hsin; Committee Member: Bakir, Muhannad; Committee Member: Lim, Sung Kyu; Committee Member: Vuduc, Richard; Committee Member: Yalamanchili, Sudhaka

VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc

Modelling and Co-simulation of hybrid vehicles: A thermal management perspective

Thermal management plays a vital role in the modern vehicle design and delivery. It enables the thermal analysis and optimisation of energy distribution to improve performance, increase efficiency and reduce emissions. Due to the complexity of the overall vehicle system, it is necessary to use a combination of simulation tools. Therefore, the co-simulation is at the centre of the design and analysis of electric, hybrid vehicles. For a holistic vehicle simulation to be realized, the simulation environment must support many physical domains. In this paper, a wide variety of system designs for modelling vehicle thermal performance are reviewed, providing an overview of necessary considerations for developing a cost-effective tool to evaluate fuel consumption and emissions across dynamic drive-cycles and under a range of weather conditions. The virtual models reviewed in this paper provide tools for component-level, system-level and control design, analysis, and optimisation. This paper concerns the latest techniques for an overall vehicle model development and software integration of multi-domain subsystems from a thermal management view and discusses the challenges presented for future studies