Third order CMOS decimator design for sigma delta modulators

A third order Cascaded Integrated Comb (CIC) filter has been designed in 0.5μm n-well CMOS process to interface with a second order oversampling sigma-delta ADC modulator. The modulator was designed earlier in 0.5μm technology. The CIC filter is designed to operate with 0 to 5V supply voltages. The modulator is operated with ±2.5V supply voltage and a fixed oversampling ratio of 64. The CIC filter designed includes integrator, differentiator blocks and a dedicated clock divider circuit, which divides the input clock by 64. The CIC filter is designed to work with an ADC that operates at a maximum oversampling clock frequency of up to 25 MHz and with baseband signal bandwidth of up to 800 kHz. The design and performance of the CIC filter fabricated has been discussed

Arquiteturas paralelas avançadas para transmissores 5G totalmente digitais

The fifth generation of mobile communications (5G) is being prepared and should be rolled out in the early coming years. Massive number of Radio-Frequency (RF) front-ends, peak data rates of 10 Gbps (everywhere and everytime), latencies lower than 10 msec and huge device densities are some of the expected disruptive capabilities. At the same time, previous generations can not be jeopardized, fostering the design of novel flexible and highly integrated radio transceivers able to support the simultaneous transmission of multi-band and multi-standard signals. The concept of all-digital transmission is being pointed out as a promising architecture to cope with such challenging requirements, due to its fully digital radio datapath. This thesis is focused on the proposal and validation of fully integrated and advanced digital transmitter architectures that excel the state-of-the-art in different figures of merit, such as transmission bandwidth, spectral purity, carrier agility, flexibility, and multi-band capability. The first part of this thesis introduces the concept of all-digital RF transmission. In particular, the foundations inherent to this thematic line are given, together with the recent advances reported in the state-of-the-art architectures.The core of this thesis, containing the main developments achieved during the Ph.D. work, is then presented and discussed. The first key contribution to the state-of-the-art is the use of cascaded Delta-Sigma (∆Σ) architectures to relax the analog filtering requirements of the conventional All-Digital Transmitters while maintaining the constant envelope waveform. Then, it is presented the first reported architecture where Antenna Arrays are directly driven by single-chip and single-bit All-Digital Transmitters, with promising results in terms of simplification of the RF front-ends and overall flexibility. Subsequently, the thesis proposes the first reported RF-stage All-Digital Transmitter that can be embedded within a single Field-Programmable Gate Array (FPGA) device. Thereupon, novel techniques to enable the design of wideband All-Digital Transmitters are reported. Finally, the design of concurrent multi-band transmitters is introduced. In particular, the design of agile and flexible dual and triple bands All-DigitalTransmitter (ADT) is demonstrated, which is a very important topic for scenarios that demand carrier aggregation. This Ph.D. contributes withseveral advances to the state-of-the-art of RF all-digital transmitters.A quinta geração de comunicações móveis (5G) está a ser preparada e deve ser comercializada nos próximos anos. Algumas das caracterı́sticas inovadoras esperadas passam pelo uso de um número massivo de font-ends de Rádio-Frequência (RF), taxas de pico de transmissão de dados de 10 Gbps (em todos os lugares e em todas as ocasiões), latências inferiores a 10 mseg e elevadas densidades de dispositivos. Ao mesmo tempo, as gerações anteriores não podem ser ignoradas, fomentando o design de novos transceptores de rádio flexı́veis e altamente integrados, capazes de suportar a transmissão simultânea de sinais multi-banda e multi-standard. O conceito de transmissão totalmente digital é considerado como um tipo de arquitetura promissora para lidar com esses requisitos desafiantes, devido ao seu datapath de rádio totalmente digital. Esta tese é focada na proposta e validação de arquiteturas de transmissores digitais totalmente integradas e avançadas que ultrapassam o estado da arte em diferentes figuras de mérito, como largura de banda de transmissão, pureza espectral, agilidade de portadora, flexibilidade e capacidade multibanda. A primeira parte desta tese introduz o conceito de transmissores de RF totalmente digitais. Em particular, os fundamentos inerentes a esta linha temática são apresentados, juntamente com os avanços mais recentes do estado-da-arte. O núcleo desta tese, contendo os principais desenvolvimentos alcançados durante o trabalho de doutoramento, é então apresentado e discutido. A primeira contribuição fundamental para o estado da arte é o uso de arquiteturas em cascata com moduladores ∆Σ para relaxar os requisitos de filtragem analógica dos transmissores RF totalmente digitais convencionais, mantendo a forma de onda envolvente constante. Em seguida, é apresentada a primeira arquitetura em que agregados de antenas são excitados diretamente por transmissores digitais de um único bit inseridos num único chip, com resultados promissores em termos de simplificação dos front-ends de RF e flexibilidade em geral. Posteriormente, é proposto o primeiro transmissor totalmente digital RF-stage relatado que pode ser incorporado dentro de um único Agregado de Células Lógicas Programáveis. Novas técnicas para permitir o desenho de transmissores RF totalmente digitais de banda larga são também apresentadas. Finalmente, o desenho de transmissores simultâneos de múltiplas bandas é exposto. Em particular, é demonstrado o desenho de transmissores de duas e três bandas ágeis e flexı́veis, que é um tópico essencial para cenários que exigem agregação de múltiplas bandas.Apoio financeiro da Fundação para a Ciência e Tecnologia (FCT) no âmbito de uma bolsa de doutoramento, ref. PD/BD/105857/2014.Programa Doutoral em Telecomunicaçõe

Design of low OSR, high precision analog-to-digital converters

Advances in electronic systems have lead to the demand for high resolution, high bandwidth Analog-to-Digital Converters (ADCs). Oversampled ADCs are well- known for high accuracy applications since they benefit from noise shaping and they usually do not need highly accurate components. However, as a consequence of oversampling, they have limited signal bandwidth. The signal bandwidth (BW) of oversampled ADCs can be increased either by increasing the sampling rate or reducing the oversampling ratio (OSR). Reducing OSR is a more promising method for increasing the BW, since the sampling speed is usually limited by the technology. The advantageous properties (e.g. low in-band quantization, relaxed accuracy requirements of components) of oversampled ADCs are usually diminished at lower OSRs and preserving these properties requires complicated and power hungry architectures. In this thesis, different combinations of delta-sigma and pipelined ADCs are explored and new techniques for designing oversampled ADCs are proposed. A Hybrid Delta-Sigma/Pipelined (HDSP) ADC is presented. This ADC uses a pipelined ADC as the quantizer of a single-loop delta-sigma modulator and benefits from the aggressive quantization of the pipelined quantizer at low OSRs. A Noise-Shaped Pipelined ADC is proposed which exploits a delta-sigma modulator as the sub-ADC of a pipeline stage to reduce the sensitivity to the analog imperfection. Three prototype ADCs were fabricated in 0.18μm CMOS technology to verify the effectiveness of the proposed techniques. The performance of these architectures is among the best reported for high bandwidth oversampled ADCs.Keywords: Delta-Sigma, Loop Filter, Oversampled ADC, Gain Stage, Pipeline, Noise Shapin

Programmable CMOS Analog-to-Digital Converter Design and Testability

In this work, a programmable second order oversampling CMOS delta-sigma analog-to-digital converter (ADC) design in 0.5µm n-well CMOS processes is presented for integration in sensor nodes for wireless sensor networks. The digital cascaded integrator comb (CIC) decimation filter is designed to operate at three different oversampling ratios of 16, 32 and 64 to give three different resolutions of 9, 12 and 14 bits, respectively which impact the power consumption of the sensor nodes. Since the major part of power consumed in the CIC decimator is by the integrators, an alternate design is introduced by inserting coder circuits and reusing the same integrators for different resolutions and oversampling ratios to reduce power consumption. The measured peak signal-to-noise ratio (SNR) for the designed second order delta-sigma modulator is 75.6dB at an oversampling ratio of 64, 62.3dB at an oversampling ratio of 32 and 45.3dB at an oversampling ratio of 16. The implementation of a built-in current sensor (BICS) which takes into account the increased background current of defect-free circuits and the effects of process variation on ΔIDDQ testing of CMOS data converters is also presented. The BICS uses frequency as the output for fault detection in CUT. A fault is detected when the output frequency deviates more than ±10% from the reference frequency. The output frequencies of the BICS for various model parameters are simulated to check for the effect of process variation on the frequency deviation. A design for on-chip testability of CMOS ADC by linear ramp histogram technique using synchronous counter as register in code detection unit (CDU) is also presented. A brief overview of the histogram technique, the formulae used to calculate the ADC parameters, the design implemented in 0.5µm n-well CMOS process, the results and effectiveness of the design are described. Registers in this design are replaced by 6T-SRAM cells and a hardware optimized on-chip testability of CMOS ADC by linear ramp histogram technique using 6T-SRAM as register in CDU is presented. The on-chip linear ramp histogram technique can be seamlessly combined with ΔIDDQ technique for improved testability, increased fault coverage and reliable operation

Multi-band Oversampled Noise Shaping Analog to Digital Conversion

Oversampled noise shaping analog to digital (A/D) converters, which are commonly known as delta-sigma (ΔΣ) converters, have the ability to convert relatively low bandwidth signals with very high resolution. Such converters achieve their high resolution by oversampling, as well as processing the signal and quantization noise with different transfer functions. The signal transfer function (STF) is typically a delay over the signal band while the noise transfer function (NTF) is designed to attenuate quantization noise in the signal band. A side effect of the NTF is an amplification of the noise outside the signal band. Thus, a digital filter subsequently attenuates the out-of-band quantization noise. The focus of this thesis is the investigation of ΔΣ architectures that increase the bandwidth where high resolution conversion can be achieved. It uses parallel architectures exploiting frequency or time slicing to meet this objective. Frequency slicing involves quantizing different portions of the signal frequency spectrum using several quantizers in parallel and then combining the results of the quantizers to form an overall result. Time slicing involves quantizing various groups of time domain signal samples with different quantizers in parallel and then combining the results of the quantizers to form an overall output. Several interesting observations can be made from this general perspective of frequency and time slicing. Although the representation of a signal are completely equivalent in time or frequency, the thesis shows that this is not the case for known frequency and time sliced A/D architectures. The performance of such systems under ideal conditions are compared for PCM as well as for ΔΣ A/D converters. A multi-band frequency sliced architecture for delta-sigma conversion is proposed and its performance is included in the above comparison. The architecture uses modulators which realize different NTFs for different portions of the signal band. Each band is converted in parallel. A bank of FIR filters attenuates the out of-band noise for each band and achieves perfect reconstruction of the signal component. A design procedure is provided for the design of the filter bank with reduced computational complexity. The use of complex NTFs in the multi-band ΔΣ architecture is also proposed. The peformance of real and complex NTFs is compared. Performance evaluations are made for ideal systems as well as systems suffering from circuit implementation imperfections such as finite opamp gain and mismatched capacitor ratios

Novel switched-capacitor circuits for delta-sigma modulators

Oversampled delta-sigma modulation is one of the widely used A/D conversion techniques for narrow bandwidth signals. In this study several new lowpass and bandpass delta-sigma modulator architectures as well as novel pseudo-N-path integrators that can be used in implementing these architectures are proposed. By using multiplexing techniques the new lowpass delta-sigma modulator architectures exchange higher clock rates with hardware complexity. For a given oversampling ratio (OSR), the multiplexed first-order delta-sigma modulator achieves a higher resolution. Guaranteed stability is a very desirable feature of these structures. The multi-loop delta-sigma modulator architecture similarly reduces the number of integrators needed to achieve high-resolution conversion for a given OSR. To ensure stability a quantizer with (N+1) bits must be used, where N is the number of loops, or in other words, the order of the delta-sigma modulator. Digital correction or randomizing techniques can be used to eliminate the performance reduction due to digital-to-analog- (D/A) converter nonlinearity error [59], [64]. Bandpass delta-sigma modulators are useful for applications such as AM radio receivers, spectrum analyzers, and digital wireless systems. Using z --> -z[superscript N] or z --> z[superscript N] mapping, a low pass delta-sigma modulator can be transformed to a bandpass one. One of the methods to implement the loop filters in bandpass delta-sigma modulators is to use Pseudo-N-Path (PNP) switched-capacitor (SC) integrators. The advantage is that the center frequency occurs exactly at an integer division of the sampling frequency because of the number of physical paths. To achieve maximum resolution, integrators that do not suffer from clock feedthrough peaks are needed. The proposed differential and single-ended novel PNP integrators address this problem [76]. To keep the opamp specifications less stringent while achieving high resolution, these PNP integrators have been further improved with gain compensation techniques [53]