Free Level Threshold Zone (FLTZ) Logic For Mixed Analog-Digital Closed Loop Circuitry [TK7887.6. N335 2008 f rb].

Para penyelidik sentiasa mencari cara-cara penambahbaikan kaedah antara muka antara domain Analog dan Digital. Researchers have always look for ways to improve the interfacing method between the Analog and Digital domain

Design of an Integrated Silicon Carbide Nonlinear-carrier PWM Controller for Boost Converter Applications

Power electronics consisting of a switch mode power supply with feedback control have a great number of applications, including many that require extreme environment capability, such as the aerospace and automotive industries. Silicon carbide (SiC) is a common material in which power devices are created for use in switch mode power supplies, such as boost converters, giving those power supplies extremely high temperature capabilities. To truly realize the temperature capabilities of SiC in power supplies, an integrated SiC converter has been designed that is also high-temperature capable. Herein, the properties of SiC integrate circuit (IC) processes are discussed and nonlinear-carrier (NLC) control is proposed as a controller topology that can work within the design challenges presented by SiC. A boost converter with an NLC controller is demonstrated in simulation with circuit blocks built entirely from SiC IC models

Um Modulador de Pulsos de Modo Misto e Baixo Consumo para Aplicação em Conversores Chaveados DC-DC.

Ainda que estudos de controladores digitais para conversores chaveados DC-DC (Switched Mode Power Supplies – SMPS) foram desenvolvidos nos últimos quinze anos, os controladores analógicos são amplamente adotados pela indústria, especialmente para aplicações portáteis (baseadas em baterias, como celulares, notebooks, tablets etc), devido aos custos e desvantagens dos controladores digitais tradicionais (alta frequência de amostragem de clock e consumo de potência). Entretanto, à medida que dispositivos eletrônicos portáteis requerem menor espaço de placa de circuito impresso (Printed Circuit Board – PCB), então o uso de componentes passivos discretos para concepção de compensadores PID analógicos começa a se tornar indesejável e, da mesma forma, o uso de componentes passivos em circuitos integrados devido ao considerável custo e área de silício. Para a solução do problema exposto, este trabalho propõe o desenvolvimento de um modulador de pulsos de modo misto (Mixed-Signal Pulse Width Modulator – MSPWM) a partir de células analógicas padrões em seu estado da arte, apresentando baixo consumo, alta precisão, alta linearidade, independência da temperatura de operação e, combinado ao uso de um compensador PID digital, torna-se desnecessário o uso de componentes passivos discretos, tornando-se uma potencial nova estratégia para aplicações portáteis

Comparación numérica y experimental de técnicas de control quasi-sliding, sliding y PID en un convertidor buck

In this paper the Sliding Mode Control (SMC), PID and ZAD (Zero Average Dynamic) strategies are applied to an electronic DC-DC power converter. Time behavior for each controller is shown for numerical solution and experimental realization. The results in SMC and PID are contrasted with a ZAD-FPIC controller combined with a recently developed strategy named FPIC (Fixed Point Induction Control). Stability in SMC is guaranteed by the Lyapunov theorem. The PID controller is designed in an analytical way using pole placement. The main problem with the physical realization was the sample and hold in the variable acquisition system, in addition to time delay introduced by the computing process. From a practical point of view, the ZAD-FPIC technique has advantages no shown by PID and SMC working with sample and hold, these advantages have been corroborated experimentally. The designs have been tested in an RCP (Rapid Control Prototyping) system based on DSP from the dSPACE platform. Both numerical performance and experimental performance agree.En este artículo son aplicadas varias técnicas de control para un convertidor reductor DC-DC estas son: control por modos deslizantes (SMC), PID y promediado de dinámica cero (ZAD). El comportamiento en el tiempo para cada controlador es mostrado tanto numéricamente como experimentalmente. Los resultados de SMC y PID son contrastados con la estrategia de control ZAD-FPIC esta última es combinada con una reciente técnica de control llama FPIC (control por inducción al punto fijo). La estabilidad de SMC es garantizada mediante teorema de Lyapunov. El control PID es diseñado de forma analítica usando desplazamiento de polos. El principal problema en la realización experimental fue la velocidad de muestreo y retención de las variables adquiridas del sistema, adicionalmente el tiempo de retardo presente en los procesos de procesamiento. Desde el punto de vista práctico la técnica de control ZAD-FPIC tiene ventajas en comparación con PID y SMC cuando se trabaja con muestreo y retención, esas ventajas han sido corroboradas experimentalmente. Los experimentos han sido probados en sistema RCP (prototipo rápido de control) específicamente en una DSP de la compañía dSPACE, al final tanto los resultados de la simulación numérica y la experimental son muy similares

Comparación numérica y experimental de técnicas de control quasi-sliding, sliding y PID en un convertidor buck

In this paper the Sliding Mode Control (SMC), PID and ZAD (Zero Average Dynamic) strategies are applied to an electronic DC-DC power converter. Time behavior for each controller is shown for numerical solution and experimental realization. The results in SMC and PID are contrasted with a ZAD-FPIC controller combined with a recently developed strategy named FPIC (Fixed Point Induction Control). Stability in SMC is guaranteed by the Lyapunov theorem. The PID controller is designed in an analytical way using pole placement. The main problem with the physical realization was the sample and hold in the variable acquisition system, in addition to time delay introduced by the computing process. From a practical point of view, the ZAD-FPIC technique has advantages no shown by PID and SMC working with sample and hold, these advantages have been corroborated experimentally. The designs have been tested in an RCP (Rapid Control Prototyping) system based on DSP from the dSPACE platform. Both numerical performance and experimental performance agree.En este artículo son aplicadas varias técnicas de control para un convertidor reductor DC-DC estas son: control por modos deslizantes (SMC), PID y promediado de dinámica cero (ZAD). El comportamiento en el tiempo para cada controlador es mostrado tanto numéricamente como experimentalmente. Los resultados de SMC y PID son contrastados con la estrategia de control ZAD-FPIC esta última es combinada con una reciente técnica de control llama FPIC (control por inducción al punto fijo). La estabilidad de SMC es garantizada mediante teorema de Lyapunov. El control PID es diseñado de forma analítica usando desplazamiento de polos. El principal problema en la realización experimental fue la velocidad de muestreo y retención de las variables adquiridas del sistema, adicionalmente el tiempo de retardo presente en los procesos de procesamiento. Desde el punto de vista práctico la técnica de control ZAD-FPIC tiene ventajas en comparación con PID y SMC cuando se trabaja con muestreo y retención, esas ventajas han sido corroboradas experimentalmente. Los experimentos han sido probados en sistema RCP (prototipo rápido de control) específicamente en una DSP de la compañía dSPACE, al final tanto los resultados de la simulación numérica y la experimental son muy similares

Variable Spurious Noise Mitigation Techniques in Hysteretic Buck Converters

This work proposes a current-mode hysteretic buck converter with a spur-free constant-cycle frequency-hopping controller that fully eliminates spurs from the switching noise spectrum irrespective of variations in the switching frequency and operating conditions. As a result, the need for frequency regulation loops to ensure non-varying switching frequency (i.e. fixed spurs location) in hysteretic controllers is eliminated. Moreover, compared to frequency regulation loops, the proposed converter offers the advantage of eliminating mixing and interference altogether due to its spur-free operation, and thus, it can be used to power, or to be integrated within noise-sensitive systems while benefiting from the superior dynamic performance of its hysteretic operation. The proposed converter uses dual-sided hysteretic band modulation to eliminate the inductor current imbalance that results from frequency hopping along with the output voltage transients and low-frequency noise floor peaking associated with it. Moreover, a feedforward adaptive hysteretic band controller is proposed to reduce variations in the switching frequency with the input voltage, and an all-digital soft-startup circuit is proposed to control the in-rush current without requiring any off-chip components. The converter is implemented in a 0.35-õm standard CMOS technology and it achieves 92% peak efficiency

Design and test of digitally-controlled power management IPs in advanced CMOS technologies

Les technologies avancées de semi-conducteur permettent de mettre en œuvre un contrôleur numérique dédié aux convertisseurs à découpage, de faible puissance et de fréquence de découpage élevée sur FPGA et ASIC. Cette thèse vise à proposer des contrôleurs numériques des performances élevées, de faible consommation énergétique et qui peuvent être implémentés facilement. En plus des contrôleurs numériques existants comme PID, RST, tri-mode et par mode de glissement, un nouveau contrôleur numérique (DDP) pour le convertisseur abaisseur de tension est proposé sur le principe de la commande prédictive: il introduit une nouvelle variable de contrôle qui est la position de la largeur d'impulsion permettant de contrôler de façon simultanée le courant dans l'inductance et la tension de sortie. La solution permet une dynamique très rapide en transitoire, aussi bien pour la variation de la charge que pour les changements de tension de référence. Les résultats expérimentaux sur FPGA vérifient les performances de ce contrôleur jusqu'à la fréquence de découpage de 4MHz. Un contrôleur numérique nécessite une modulation numérique de largeur d'impulsion (DPWM). L'approche Sigma-Delta de la DPWM est un bon candidat en ce qui concerne le compromis entre la complexité et les performances. Un guide de conception d'étage Sigma-Delta pour le DPWM est présenté. Une architecture améliorée de traditionnelles 1-1 MASH Sigma-Delta DPWM est synthétisée sans détérioration de la stabilité en boucle fermée ainsi qu'en préservant un coût raisonnable en ressources matérielles. Les résultats expérimentaux sur FPGA vérifient les performances des DPWM proposées en régimes stationnaire et transitoire. Deux ASICs sont portés en CMOS 0,35 m: le contrôleur en tri-mode pour le convertisseur abaisseur de tension et la commande par mode de glissement pour les convertisseurs abaisseur et élévateur de tension. Les bancs de test sont conçus pour conduire à un modèle d'évaluation de consommation énergétique. Pour le contrôleur en tri-mode, la consommation de puissance mesurée est seulement de 24,56mW/MHz lorsque le ratio de temps en régime de repos (stand-by) est 0,7. Les consommations de puissance de command par mode de glissement pour les convertisseurs abaisseur et élévateur de tension sont respectivement de 4,46mW/MHz et 4,79mW/MHz. En utilisant le modèle de puissance, une consommation de la puissance estimée inférieure à 1mW/MHz est envisageable dans des technologies CMOS plus avancées. Comparé aux contrôlés homologues analogiques de l'état de l'art, les prototypes ASICs illustrent la possibilité d'atteindre un rendement comparable pour les applications de faible et de moyen puissance mais avec l'avantage d'une meilleure précision et une meilleure flexibilité.Owing to the development of modern semiconductor technology, it is possible to implement a digital controller for low-power high switching frequency DC-DC power converter in FPGA and ASIC. This thesis is intended to propose digital controllers with high performance, low power consumption and simple implementation architecture. Besides existing digital control-laws, such as PID, RST, tri-mode and sliding-mode (SM), a novel digital control-law, direct control with dual-state-variable prediction (DDP control), for the buck converter is proposed based on the principle of predictive control. Compared to traditional current-mode predictive control, the predictions of the inductor current and the output voltage are performed at the same time by adding a control variable to the DPWM signal. DDP control exhibits very high dynamic transient performances under both load variations and reference changes. Experimental results in FPGA verify the performances at switching frequency up to 4MHz. For the boost converter exhibiting more serious nonlinearity, linear PID and nonlinear SM controllers are designed and implemented in FPGA to verify the performances. A digital control requires a DPWM. Sigma-Delta DPWM is therefore a good candidate regarding the implementation complexity and performances. An idle-tone free condition for Sigma-Delta DPWM is considered to reduce the inherent tone-noise under DC-excitation compared to the classic approach. A guideline for Sigma-Delta DPWM helps to satisfy proposed condition. In addition, an 1-1 MASH Sigma-Delta DPWM with a feasible dither generation module is proposed to further restrain the idle-tone effect without deteriorating the closed-loop stability as well as to preserve a reasonable cost in hardware resources. The FPGA-based experimental results verify the performances of proposed DPWM in steady-state and transient-state. Two ASICs in 0.35 m CMOS process are implemented including the tri-mode controller for buck converter and the PID and SM controllers for the buck and boost converters respectively. The lab-scale tests are designed to lead to a power assessment model suggesting feasible applications. For the tri-mode controller, the measured power consumption is only 24.56mW/MHz when the time ratio of stand-by operation mode is 0.7. As specific power optimization strategies in RTL and system-level are applied to the latter chip, the measured power consumptions of the SM controllers for buck converter and boost converter are 4.46mW/MHz and 4.79mW/MHz respectively. The power consumption is foreseen as less than 1mW/MHz when the process scales down to nanometer technologies based on the power-scaling model. Compared to the state-of-the-art analog counterpart, the prototype ICs are proven to achieve comparable or even higher power efficiency for low-to-medium power applications with the benefit of better accuracy and better flexibility.VILLEURBANNE-DOC'INSA-Bib. elec. (692669901) / SudocSudocFranceF

Analysis on Supercapacitor Assisted Low Dropout (SCALDO) Regulators

State-of-the-art electronic systems employ three fundamental techniques for DC-DC converters: (a) switch-mode power supplies (SMPS); (b) linear power supplies; (c) switched capacitor (charge pump) converters. In practical systems, these three techniques are mixed to provide a complex, but elegant, overall solution, with energy efficiency, effective PCB footprint, noise and transient performance to suit different electronic circuit blocks. Switching regulators have relatively high end-to-end efficiency, in the range of 70 to 93%, but can have issues with output noise and EMI/RFI emissions. Switched capacitor converters use a set of capacitors for energy storage and conversion. In general, linear regulators have low efficiencies in the range 30 to 60%. However, they have outstanding output characteristics such as low noise, excellent transient response to load current fluctuations, design simplicity and low cost design which are far superior to SMPS. Given the complex situation in switch-mode converters, low dropout (LDO) regulators were introduced to address the equirements of noise-sensitive and fast transient loads in portable devices. A typical commercial off-the-shelf LDO has its input voltage slightly higher than the desired regulated output for optimal efficiency. The approximate efficiency of a linear regulator, if the power consumed by the control circuits is negligible, can be expressed by the ratio of Vo/Vin. A very low frequency supercapacitor circulation technique can be combined with commercial low dropout regulator ICs to significantly increase the end-to-end efficiency by a multiplication factor in the range of 1.33 to 3, compared to the efficiency of a linear regulator circuit with the same input-output voltages. In this patented supercapacitor-assisted low dropout (SCALDO) regulator technique developed by a research team at the University of Waikato, supercapacitors are used as lossless voltage droppers, and the energy reuse occurs at very low frequencies in the range of less than ten hertz, eliminating RFI/EMI concerns. This SCALDO technique opens up a new approach to design step-down, DC-DC converters suitable for processor power supplies with very high end-to-end efficiency which is closer to the efficiencies of practical switching regulators, while maintaining the superior output specifications of a linear design. Furthermore, it is important to emphasize that the SCALDO technique is not a variation of well-known switched capacitor DC-DC converters. In this thesis, the basic SCALDO concept is further developed to achieve generalised topologies, with the relevant theory that can be applied to a converter with any input-output step-down voltage combination. For these generalised topologies, some important design parameters, such as the number of supercapacitors, switching matrix details and efficiency improvement factors, are derived to form the basis of designing SCALDO regulators. With the availability of commercial LDO ICs with output current ratings up to 10 A, and thin-prole supercapacitors with DC voltage ratings from 2.3 to 5.5 V, several practically useful, medium-current SCALDO prototypes: 12V-to-5V, 5V-to-2V, 5.5V-to-3.3V have been developed. Experimental studies were carried out on these SCALDO prototypes to quantify performance in terms of line regulation, load regulation, efficiency and transient response. In order to accurately predict the performance and associated waveforms of the individual phases (charge, discharge and transition) of the SCALDO regulator, Laplace transform-based theory for supercapacitor circulation is developed, and analytical predictions are compared with experimental measurements for a 12V-to-5V prototype. The analytical results tallied well with the practical waveforms observed in a 12V-to-5V converter, indicating that the SCALDO technique can be generalized to other versatile configurations, and confirming that the simplified assumptions used to describe the circuit elements are reasonable and justifiable. After analysing the performance of several SCALDO prototypes, some practical issues in designing SCALDO regulators have been identified. These relate to power losses and implications for future development of the SCALDO design