1 V CMOS subthreshold log domain PDM

A new CMOS circuit strategy for very low-voltage Pulse-Duration Modulators (PDM) is proposed. Optimization of voltage supply scaling below the sum of threshold voltages is based on Instantaneous Log Companding processing through the MOSFET operating in weak inversion. A 1 V VLSI PDM circuit for very low-voltage audio applications such as Hearing Aids is presented, showing good agreement between simulated and experimental data.Comisión Interministerial de Ciencia y Tecnología TIC97-1159, TIC99-1084European Union 2306

Low-voltage CMOS log-companding techniques for audio applications

This paper presents a collection of novel current-mode circuit techniques for the integration of very low-voltage (down to 1 V) low-power (few hundreds of μA) complete SoCs in CMOS technologies. The new design proposal is based on both, the Log Companding theory and the MOSFET operating in subthreshold. Several basic building blocks for audio amplification, AGC and arbitrary filtering are given. The feasibility of the proposed CMOS circuits is illustrated through experimental data for different design case studies in 1.2 and 0.35 μm VLSI technologies.Comisión Interministerial de Ciencia y Tecnología TIC97-1159, TIC99- 1084European Union ESPRIT-FUSE-2306

A 6-bit, two-step, successive approximation logarithmic ADC for biomedical applications

This paper presents the design and realization of a novel low-power 6-bit successive approximation logarithmic ADC for biomedical applications. A two-step successive approximation method is proposed to obtain a piecewise-linear approximation of the desired logarithmic transfer function. The proposed ADC has been designed and simulated using process parameters from a standard 0.35 μm 2P4M CMOS technology with a single 1.8 V power supply voltage. Simulation results show that, at a sampling rate of 25 kS/s, the proposed ADC consumes 4.36 μW to 14.6 μW (proportional to input amplitudes). The proposed ADC achieves 18.6 pJ/conversion-step, maximum INL of 0.45 LSB, an ENOB of 4.97-bits, and SNDR of 31.7 dB with 1 V full-scale input range

DESIGN OF PC-PROGRAMMABLE DIGITAL HEARING-TESTING DEVICE

Abstrac

Analog adaptive nonlinear filtering and spectral analysis for low-power audio applications

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, September 2006."August 2006."Includes bibliographical references.Filters are one of the basic building blocks of analog circuits. For linear operation, the power consumption is proportional to the dynamic range for a given topology. I have explored techniques to lower the power consumption below this limit by extending operation beyond the linear range. First, I built a power-efficient linear gm-C filter that demonstrates that dynamic range can be shifted to higher linear ranges using capacitive attenuation. In a standard gm-C filter, the minimum noise is limited by the discrete charge on the electrons and holes stored on the capacitor. This noise can only be reduced by collecting more charge on a larger capacitor, consuming more power. The maximum signal is determined by the linear range of the transconductor. This work showed that both the noise and the maximum signal can be amplified by including a capacitive attenuator in the feedback path of filter. In order to increase the dynamic range, I explored the non-linear operation of the filters, including jump resonance. Unlike harmonic distortion and gain compression which slowly increase with the input amplitude, jump resonance is not present in a linear system, but develops in the presence of strong nonlinearity.(cont.) It is characterized by a discontinuous jump in the frequency response near the resonant peak. I have analyzed the behavior using both describing function and state-space techniques. Then, I developed a novel graphical analysis technique. Finally, I design, built, and tested a circuit for avoiding jump resonance for audio filters. Finally, I took advantage of nonlinearities in a filtering system to build a micropower companding speech processor. This system implements the companding speech processing algorithm to improve speech comprehension in moderate noise environments. The sixteen channel system increases the spectral contrast of speech signals by performing an adjustable two-tone suppression function, replacing the function of a normally function cochlea for hearing aid or cochlear implant users. The system runs on less than 60uW of power, a consumption so low it could run for 6 months on a standard hearing aid battery.by Christopher D. Salthouse.Ph.D

Neurocomputing systems for auditory processing

This thesis studies neural computation models and neuromorphic implementations of the auditory pathway with applications to cochlear implants and artificial auditory sensory and processing systems. Very low power analogue computation is addressed through the design of micropower analogue building blocks and an auditory preprocessing module targeted at cochlear implants. The analogue building blocks have been fabricated and tested in a standard Complementary Metal Oxide Silicon (CMOS) process. The auditory pre-processing module design is based on the cochlea signal processing mechanisms and low power microelectronic design methodologies. Compared to existing preprocessing techniques used in cochlear implants, the proposed design has a wider dynamic range and lower power consumption. Furthermore, it provides the phase coding as well as the place coding information that are necessary for enhanced functionality in future cochlear implants. The thesis presents neural computation based approaches to a number of signal-processing problems encountered in cochlear implants. Techniques that can improve the performance of existing devices are also presented. Neural network based models for loudness mapping and pattern recognition based channel selection strategies are described. Compared with state—of—the—art commercial cochlear implants, the thesis results show that the proposed channel selection model produces superior speech sound qualities; and the proposed loudness mapping model consumes substantially smaller amounts of memory. Aside from the applications in cochlear implants, this thesis describes a biologically plausible computational model of the auditory pathways to the superior colliculus based on current neurophysiological findings. The model encapsulates interaural time difference, interaural spectral difference, monaural pathway and auditory space map tuning in the inferior colliculus. A biologically plausible Hebbian-like learning rule is proposed for auditory space neural map tuning, and a reinforcement learning method is used for map alignment with other sensory space maps through activity independent cues. The validity of the proposed auditory pathway model has been verified by simulation using synthetic data. Further, a complete biologically inspired auditory simulation system is implemented in software. The system incorporates models of the external ear, the cochlea, as well as the proposed auditory pathway model. The proposed implementation can mimic the biological auditory sensory system to generate an auditory space map from 3—D sounds. A large amount of real 3-D sound signals including broadband White noise, click noise and speech are used in the simulation experiments. The efiect of the auditory space map developmental plasticity is examined by simulating early auditory space map formation and auditory space map alignment with a distorted visual sensory map. Detailed simulation methods, procedures and results are presented

Ultra low power circuits for a miniature apnoea detection device

Imperial Users onl