A 60 pW g(m)C Continuous Wavelet Transform Circuit for Portable EEG Systems

Accepted versio

A Tissue Impedance Measurement Chip for Myocardial Ischemia Detection

In this paper, the design of a specific integrated circuit for the measurement of tissue impedances is presented. The circuit will be part of a multi-micro-sensor system intended to be used in cardiac surgery for sensing biomedical parameters in living bodies. Myocardium tissue impedance is one of these parameters which allows ischemia detection. The designed chip will be used in a four-electrode based setup where the effect of electrode interfaces are cancelled by design. The chip includes a circuit to generate the stimulus signals (sinusoidal current) and the circuitry to measure the magnitude and phase of the tissue impedance. Several integrated circuits have been designed, fabricated and tested, in a 0.8- m CMOS process, working at 3 V of power supply. Some of them including building blocks, and other with the whole measurement system. Experimental tests have shown the circuit feasibility giving expected results for both in-vitro and in-vivo test conditions

Low-voltage CMOS log-companding techniques for audio applications

This paper presents a collection of novel current-mode circuit techniques for the integration of very low-voltage (down to 1 V) low-power (few hundreds of μA) complete SoCs in CMOS technologies. The new design proposal is based on both, the Log Companding theory and the MOSFET operating in subthreshold. Several basic building blocks for audio amplification, AGC and arbitrary filtering are given. The feasibility of the proposed CMOS circuits is illustrated through experimental data for different design case studies in 1.2 and 0.35 μm VLSI technologies.Comisión Interministerial de Ciencia y Tecnología TIC97-1159, TIC99- 1084European Union ESPRIT-FUSE-2306

A CMOS VLSI cochlea

An engineered system that hears, such as a speech recognizer, can be designed by modeling the cochlea, or inner ear, and higher levels of the auditory nervous system. To be useful in such a system, a model of the cochlea should incorporate a variety of known effects, such as an asymmetric lowpass/bandpass response at each output channel, a short ringing time, and active adaptation to a wide range of input signal levels. An analog electronic cochlea has been built in CMOS VLSI technology using micropower techniques to achieve this goal of usefulness via realism. The key point of the model and circuit is that a cascade of simple, nearly linear, second-order filter stages with controllable Q parameters suffices to capture the physics of the fluid-dynamic traveling-wave system in the cochlea, including the effects of adaptation and active gain involving the outer hair cells. Measurements on the test chip suggest that the circuit matches both the theory and observations from real cochleas

Power-efficient current-mode analog circuits for highly integrated ultra low power wireless transceivers

In this thesis, current-mode low-voltage and low-power techniques have been applied to implement novel analog circuits for zero-IF receiver backend design, focusing on amplification, filtering and detection stages. The structure of the thesis follows a bottom-up scheme: basic techniques at device level for low voltage low power operation are proposed in the first place, followed by novel circuit topologies at cell level, and finally the achievement of new designs at system level. At device level the main contribution of this work is the employment of Floating-Gate (FG) and Quasi-Floating-Gate (QFG) transistors in order to reduce the power consumption. New current-mode basic topologies are proposed at cell level: current mirrors and current conveyors. Different topologies for low-power or high performance operation are shown, being these circuits the base for the system level designs. At system level, novel current-mode amplification, filtering and detection stages using the former mentioned basic cells are proposed. The presented current-mode filter makes use of companding techniques to achieve high dynamic range and very low power consumption with for a very wide tuning range. The amplification stage avoids gain bandwidth product achieving a constant bandwidth for different gain configurations using a non-linear active feedback network, which also makes possible to tune the bandwidth. Finally, the proposed current zero-crossing detector represents a very power efficient mixed signal detector for phase modulations. All these designs contribute to the design of very low power compact Zero-IF wireless receivers. The proposed circuits have been fabricated using a 0.5μm double-poly n-well CMOS technology, and the corresponding measurement results are provided and analyzed to validate their operation. On top of that, theoretical analysis has been done to fully explore the potential of the resulting circuits and systems in the scenario of low-power low-voltage applications.Programa Oficial de Doctorado en Tecnologías de las Comunicaciones (RD 1393/2007)Komunikazioen Teknologietako Doktoretza Programa Ofiziala (ED 1393/2007

A fully integrated physical activity sensing circuit for implantable pacemakers

PostprintThis paper shows the implementation of a fully integrated Gm-C 0.5-7Hz bandpass filter-amplifier with gain G=400, for a piezoelectric accelerometer which is part of a rate adaptive pacemaker. The fabricated circuit operates up to 2V power supply, consumes only 230nA current, and achives 2.1μVrms input noise. Detailed circuit specifications, measurements, and a comparative analysis of the system performance are presented