High-Performance, Scalable Optical Network-On-Chip Architectures

The rapid advance of technology enables a large number of processing cores to be integrated into a single chip which is called a Chip Multiprocessor (CMP) or a Multiprocessor System-on-Chip (MPSoC) design. The on-chip interconnection network, which is the communication infrastructure for these processing cores, plays a central role in a many-core system. With the continuously increasing complexity of many-core systems, traditional metallic wired electronic networks-on-chip (NoC) became a bottleneck because of the unbearable latency in data transmission and extremely high energy consumption on chip. Optical networks-on-chip (ONoC) has been proposed as a promising alternative paradigm for electronic NoC with the benefits of optical signaling communication such as extremely high bandwidth, negligible latency, and low power consumption. This dissertation focus on the design of high-performance and scalable ONoC architectures and the contributions are highlighted as follow: 1. A micro-ring resonator (MRR)-based Generic Wavelength-routed Optical Router (GWOR) is proposed. A method for developing any sized GWOR is introduced. GWOR is a scalable non-blocking ONoC architecture with simple structure, low cost and high power efficiency compared to existing ONoC designs. 2. To expand the bandwidth and improve the fault tolerance of the GWOR, a redundant GWOR architecture is designed by cascading different type of GWORs into one network. 3. The redundant GWOR built with MRR-based comb switches is proposed. Comb switches can expand the bandwidth while keep the topology of GWOR unchanged by replacing the general MRRs with comb switches. 4. A butterfly fat tree (BFT)-based hybrid optoelectronic NoC (HONoC) architecture is developed in which GWORs are used for global communication and electronic routers are used for local communication. The proposed HONoC uses less numbers of electronic routers and links than its counterpart of electronic BFT-based NoC. It takes the advantages of GWOR in optical communication and BFT in non-uniform traffic communication and three-dimension (3D) implementation. 5. A cycle-accurate NoC simulator is developed to evaluate the performance of proposed HONoC architectures. It is a comprehensive platform that can simulate both electronic and optical NoCs. Different size HONoC architectures are evaluated in terms of throughput, latency and energy dissipation. Simulation results confirm that HONoC achieves good network performance with lower power consumption

Cycle-accurate evaluation of reconfigurable photonic networks-on-chip

There is little doubt that the most important limiting factors of the performance of next-generation Chip Multiprocessors (CMPs) will be the power efficiency and the available communication speed between cores. Photonic Networks-on-Chip (NoCs) have been suggested as a viable route to relieve the off- and on-chip interconnection bottleneck. Low-loss integrated optical waveguides can transport very high-speed data signals over longer distances as compared to on-chip electrical signaling. In addition, with the development of silicon microrings, photonic switches can be integrated to route signals in a data-transparent way. Although several photonic NoC proposals exist, their use is often limited to the communication of large data messages due to a relatively long set-up time of the photonic channels. In this work, we evaluate a reconfigurable photonic NoC in which the topology is adapted automatically (on a microsecond scale) to the evolving traffic situation by use of silicon microrings. To evaluate this system's performance, the proposed architecture has been implemented in a detailed full-system cycle-accurate simulator which is capable of generating realistic workloads and traffic patterns. In addition, a model was developed to estimate the power consumption of the full interconnection network which was compared with other photonic and electrical NoC solutions. We find that our proposed network architecture significantly lowers the average memory access latency (35% reduction) while only generating a modest increase in power consumption (20%), compared to a conventional concentrated mesh electrical signaling approach. When comparing our solution to high-speed circuit-switched photonic NoCs, long photonic channel set-up times can be tolerated which makes our approach directly applicable to current shared-memory CMPs

Crosstalk Noise Aware System For WDM-Based Optical Network on Chip

Network on chip (NoC) is presented as a promising solution to face off the growing up of the data exchange in the multiprocessor system-on-chip (MPSoC). However, the traditional NoC faces two main problems: the bandwidth and the energy consumption. To face off these problems, a new technology in MPSoC, namely, optical network-on-chip (ONoC) has been introduced which it uses the optical communication to guaranty a high performance in communication between cores. In addition, wavelength division multiplexing (WDM) is exploited in ONoC to reach a high rate of bandwidth. Nevertheless, the transparency nature of the ONoC components induce crosstalk noise to the optical signals, which it has a direct effect to the signal-to-noise ratio (SNR) then decrease the performance of the ONoC. In this paper, we proposed a new system to control these impairments in the network in order to detect and monitor crosstalk noise in WDM-based ONoC. Furthermore, the crosstalk monitoring system is a distributed hardware system designed and test with the different optical components according the various network topology used in ONoC. The register-transfer level (RTL) hardware design and implementation of this system can result in high reliability, scalability and efficiency with running time less than 20 ms

Crosstalk Noise Aware System For WDM-Based Optical Network on Chip

Network on chip (NoC) is presented as a promising solution to face off the growing up of the data exchange in the multiprocessor system-on-chip (MPSoC). However, the traditional NoC faces two main problems: the bandwidth and the energy consumption. To face off these problems, a new technology in MPSoC, namely, optical network-on-chip (ONoC) has been introduced which it uses the optical communication to guaranty a high performance in communication between cores. In addition, wavelength division multiplexing (WDM) is exploited in ONoC to reach a high rate of bandwidth. Nevertheless, the transparency nature of the ONoC components induce crosstalk noise to the optical signals, which it has a direct effect to the signal-to-noise ratio (SNR) then decrease the performance of the ONoC. In this paper, we proposed a new system to control these impairments in the network in order to detect and monitor crosstalk noise in WDM-based ONoC. Furthermore, the crosstalk monitoring system is a distributed hardware system designed and test with the different optical components according the various network topology used in ONoC. The register-transfer level (RTL) hardware design and implementation of this system can result in high reliability, scalability and efficiency with running time less than 20 ms

Detection and Monitoring Intra/Inter Crosstalk in Optical Network on Chip

Multiprocessor system-on-chip (MPSoC) has become an attractive solution for improving the performance of single chip in objective to satisfy the performance growing exponentially of the computer applications as multimedia applications. However, the communication between the different processors’ cores presents the first challenge front the high performance of MPSoC. Besides, Network on Chip (NoC) is among the most prominent solution for handling the on-chip communication. Besides, NoC potential limited by physical limitation, power consumption, latency and bandwidth in the both case: increasing data exchange or scalability of Multicores. Optical communication offers a wider bandwidth and lower power consumption, based on, a new technology named Optical Network-on-Chip (ONoC) has been introduced in MPSoC. However, ONoC components induce the crosstalk noise in the network on both forms intra/inter crosstalk. This serious problem deteriorates the quality of signals and degrades network performance. As a result, detection and monitoring the impairments becoming a challenge to keep the performance in the ONoC. In this article, we propose a new system to detect and monitor the crosstalk noise in ONoC. Particularly, we present an analytic model of intra/inter crosstalk at the optical devices. Then, we evaluate these impairments in objective to present the motivation to detect and monitor crosstalk in ONoC, in which our system has the capability to detect, to localize, and to monitor the crosstalk noise in the whole network. This system offers high reliability, scalability and efficiency with time running time less than 20 ms

Simulation Of Multi-core Systems And Interconnections And Evaluation Of Fat-Mesh Networks

Simulators are very important in computer architecture research as they enable the exploration of new architectures to obtain detailed performance evaluation without building costly physical hardware. Simulation is even more critical to study future many-core architectures as it provides the opportunity to assess currently non-existing computer systems. In this thesis, a multiprocessor simulator is presented based on a cycle accurate architecture simulator called SESC. The shared L2 cache system is extended into a distributed shared cache (DSC) with a directory-based cache coherency protocol. A mesh network module is extended and integrated into SESC to replace the bus for scalable inter-processor communication. While these efforts complete an extended multiprocessor simulation infrastructure, two interconnection enhancements are proposed and evaluated. A novel non-uniform fat-mesh network structure similar to the idea of fat-tree is proposed. This non-uniform mesh network takes advantage of the average traffic pattern, typically all-to-all in DSC, to dedicate additional links for connections with heavy traffic (e.g., near the center) and fewer links for lighter traffic (e.g., near the periphery). Two fat-mesh schemes are implemented based on different routing algorithms. Analytical fat-mesh models are constructed by presenting the expressions for the traffic requirements of personalized all-to-all traffic. Performance improvements over the uniform mesh are demonstrated in the results from the simulator. A hybrid network consisting of one packet switching plane and multiple circuit switching planes is constructed as the second enhancement. The circuit switching planes provide fast paths between neighbors with heavy communication traffic. A compiler technique that abstracts the symbolic expressions of benchmarks' communication patterns can be used to help facilitate the circuit establishment

Low-power reconfigurable network architecture for on-chip photonic interconnects

Photonic Networks-On-Chip have emerged as a viable solution for interconnecting multicore computer architectures in a power-efficient manner. Current architectures focus on large messages, however, which are not compatible with the coherence traffic found on chip multiprocessor networks. In this paper, we introduce a reconfigurable optical interconnect in which the topology is adapted automatically to the evolving traffic situation. This allows a large fraction of the (short) coherence messages to use the optical links, making our technique a better match for CMP networks when compared to existing solutions. We also evaluate the performance and power efficiency of our architecture using an assumed physical implementation based on ultra-low power optical switching devices and under realistic traffic load conditions

On-Chip Optical Interconnection Networks for Multi/Manycore Architectures

The rapid development of multi/manycore technologies offers the opportunity for highly parallel architectures implemented on a single chip. While the first, low-parallelism multicore products have been based on simple interconnection structures (single bus, very simple crossbar), the emerging highly parallel architectures will require complex, limited-degree interconnection networks. This thesis studies this trend according to the general theory of interconnection structures for parallel machines, and investigates some solutions in terms of performance, cost, fault-tolerance, and run-time support to shared-memory and/or message passing programming mechanisms

Tree-structured small-world connected wireless network-on-chip with adaptive routing

Traditional Network-on-Chip (NoC) systems comprised of many cores suffer from debilitating bottlenecks of latency and significant power dissipation due to the overhead inherent in multi-hop communication. In addition, these systems remain vulnerable to malicious circuitry incorporated into the design by untrustworthy vendors in a world where complex multi-stage design and manufacturing processes require the collective specialized services of a variety of contractors. This thesis proposes a novel small-world tree-based network-on-chip (SWTNoC) structure designed for high throughput, acceptable energy consumption, and resiliency to attacks and node failures resulting from the insertion of hardware Trojans. This tree-based implementation was devised as a means of reducing average network hop count, providing a large degree of local connectivity, and effective long-range connectivity by means of a novel wireless link approach based on carbon nanotube (CNT) antenna design. Network resiliency is achieved by means of a devised adaptive routing algorithm implemented to work with TRAIN (Tree-based Routing Architecture for Irregular Networks). Comparisons are drawn with benchmark architectures with optimized wireless link placement by means of the simulated annealing (SA) metaheuristic. Experimental results demonstrate a 21% throughput improvement and a 23% reduction in dissipated energy per packet over the closest competing architecture. Similar trends are observed at increasing system sizes. In addition, the SWTNoC maintains this throughput and energy advantage in the presence of a fault introduced into the system. By designing a hierarchical topology and designating a higher level of importance on a subset of the nodes, much higher network throughput can be attained while simultaneously guaranteeing deadlock freedom as well as a high degree of resiliency and fault-tolerance

Network-on-Chip

Limitations of bus-based interconnections related to scalability, latency, bandwidth, and power consumption for supporting the related huge number of on-chip resources result in a communication bottleneck. These challenges can be efficiently addressed with the implementation of a network-on-chip (NoC) system. This book gives a detailed analysis of various on-chip communication architectures and covers different areas of NoCs such as potentials, architecture, technical challenges, optimization, design explorations, and research directions. In addition, it discusses current and future trends that could make an impactful and meaningful contribution to the research and design of on-chip communications and NoC systems