Low-noise Amplifier for Neural Recording

With a combination of engineering approaches and neurophysiological knowledge of the central nervous system, a new generation of medical devices is being developed to link groups of neurons with microelectronic systems. By doing this, researchers are acquiring fundamental knowledge of the mechanisms of disease and innovating treatments for disabilities in patients who have a failure of communication along neural pathways. A low-noise and low-power analog front-end circuit is one of the primary requirements for neural recording. The main function for the front-end amplifier is to provide gain over the bandwidth of neural signals and to reject undesired frequency components. The chip developed in this thesis is a field-programmable analog front-end amplifier consisting of 16 programmable channels with tunable frequency response. A capacitively coupled two-stage amplifier is used. The first-stage amplifier is a Low-Noise Amplifier (LNA), as it directly interfaces with the neural recording micro-electrodes; the second stage is a high gain and high swing amplifier. A MOS resistor in the feedback path is used to get tunable low-cut-off frequency and reject the dc offset voltage. Our design builds upon previous recording chips designed by two former graduate stu- dents in our lab. In our design, the circuits are optimized for low noise. Our simulations show the recording channel has a gain of 77.9 dB and input-referred noise of 6.95 µV rms(Root-Mean-Square voltage) over 750 Hz to 6.9 kHz. The chip is fabricated in AMS 0.35 µm CMOS technology for a total die area of 3 x 3 mm 2 and Total Power Dissipation (TPD) of 2.9 mW. To verify the functionality and adherence to the design specifications it will be tested on Printed-Circuit-Board

A neural probe with up to 966 electrodes and up to 384 configurable channels in 0.13 μm SOI CMOS

In vivo recording of neural action-potential and local-field-potential signals requires the use of high-resolution penetrating probes. Several international initiatives to better understand the brain are driving technology efforts towards maximizing the number of recording sites while minimizing the neural probe dimensions. We designed and fabricated (0.13-μm SOI Al CMOS) a 384-channel configurable neural probe for large-scale in vivo recording of neural signals. Up to 966 selectable active electrodes were integrated along an implantable shank (70 μm wide, 10 mm long, 20 μm thick), achieving a crosstalk of −64.4 dB. The probe base (5 × 9 mm2) implements dual-band recording and a 1

A power efficient neural spike recording channel with data bandwidth reduction

This paper presents a mixed-signal neural spike recording channel which features, as an added value, a simple and low-power data compression mechanism. The channel uses a band-limited differential low noise amplifier and a binary search data converter, together with other digital and analog blocks for control, programming and spike characterization. The channel offers a self-calibration operation mode and it can be configured both for signal tracking (to raw digitize the acquired neural waveform) and feature extraction (to build a first-order PWL approximation of the spikes). The prototype has been fabricated in a standard CMOS 0.13μm and occupies 400μm×400μm. The overall power consumption of the channel during signal tracking is 2.8μW and increases to 3.0μW average when the feature extraction operation mode is programmed.Ministerio de Ciencia e Innovación TEC2009-08447Junta de Andalucía TIC-0281

A 4-mode reconfigurable low noise amplifier for implantable neural recording channels

In this paper a reconfigurable implantable low noise amplifier for the recording of neural signals is presented. It is comprised by low-power and noise efficient current reuse OTAs in its direct path. The proposed architecture allows for an active feedback to set the high-pass corner in place of the commonly used pseudoresistor. Bandwidth selectivity is achieved by circuit reconfigurability which changes the pole frequencies of the system without impacting the total power consumption. Simulation results in AMS 0.18μm technology validate the proposed architecture in both nominal and corner process conditions with an estimated total power consumption of 454nW.Office of Naval Research (USA) N00014-14-1-0355Junta de Andalucía TIC 233

An Ultra-Low-Power Front-End Neural Interface with Automatic Gain for Uncalibrated Monitoring

Accepted versio

Active C4 electrodes for local field potential recording applications

Extracellular neural recording, with multi-electrode arrays (MEAs), is a powerful method used to study neural function at the network level. However, in a high density array, it can be costly and time consuming to integrate the active circuit with the expensive electrodes. In this paper, we present a 4 mm × 4 mm neural recording integrated circuit (IC) chip, utilizing IBM C4 bumps as recording electrodes, which enable a seamless active chip and electrode integration. The IC chip was designed and fabricated in a 0.13 μm BiCMOS process for both in vitro and in vivo applications. It has an input-referred noise of 4.6 μV rms for the bandwidth of 10 Hz to 10 kHz and a power dissipation of 11.25 mW at 2.5 V, or 43.9 μW per input channel. This prototype is scalable for implementing larger number and higher density electrode arrays. To validate the functionality of the chip, electrical testing results and acute in vivo recordings from a rat barrel cortex are presented.R01 NS072385 - NINDS NIH HHS; 1R01 NS072385 - NINDS NIH HH

A self-calibration circuit for a neural spike recording channel

This paper presents a self-calibration circuit for a neural spike recording channel. The proposed design tunes the bandwidth of the signal acquisition Band-Pass Filter (BPF), which suffers from process variations corners. It also performs the adjustment of the Programmable Gain Amplifier (PGA) gain to maximize the input voltage range of the analog-to-digital conversion. The circuit, which consists on a frequency-controlled signal generator and a digital processor, operates in foreground, is completely autonomous and integrable in an estimated area of 0.026mm 2 , with a power consumption around 450nW. The calibration procedure takes less than 250ms to select the configuration whose performance is closest to the required one.Ministerio de Ciencia e Innovación TEC2009-08447Junta de Andalucía TIC-0281

700mV low power low noise implantable neural recording system design

This dissertation presents the work for design and implementation of a low power, low noise neural recording system consisting of Bandpass Amplifier and Pipelined Analog to Digital Converter (ADC) for recording neural signal activities. A low power, low noise two stage neural amplifier for use in an intelligent Radio-Frequency Identification (RFID) based on folded cascode Operational Transconductance Amplifier (OTA) is utilized to amplify the neural signals. The optimization of the number of amplifier stages is discussed to achieve the minimum power and area consumption. The amplifier power supply is 0.7V. The midband gain of amplifier is 58.4dB with a 3dB bandwidth from 0.71 to 8.26 kHz. Measured input-referred noise and total power consumption are 20.7 μVrms and 1.90 μW respectively. The measured result shows that the optimizing the number of stages can achieve lower power consumption and demonstrates the neural amplifier's suitability for instu neutral activity recording. The advantage of power consumption of Pipelined ADC over Successive Approximation Register (SAR) ADC and Delta-Sigma ADC is discussed. An 8 bit fully differential (FD) Pipeline ADC for use in a smart RFID is presented in this dissertation. The Multiplying Digital to Analog Converter (MDAC) utilizes a novel offset cancellation technique robust to device leakage to reduce the input drift voltage. Simulation results of static and dynamic performance show this low power Pipeline ADC is suitable for multi-channel neural recording applications. The performance of all proposed building blocks is verified through test chips fabricated in IBM 180nm CMOS process. Both bench-top and real animal test results demonstrate the system's capability of recording neural signals for neural spike detection

Wireless integrated circuit for the acquisition of electrocorticogram signals

Journal ArticleAbstract-We present the design and characterization of amplifiers and control logic for an integrated circuit designed to record electrocorticograms (ECoG) from the surface of the brain. The chip, which was fabricated in a 0.6-μm BiCMOS process, contains 100 amplifiers, control logic, and circuits for wireless power and transmission of data. ECoG signals, sensed by electrodes, are capacitively coupled to the amplifiers. Each amplifier has a gain of 59.2 dB, a maximum bandwidth of 240 Hz, an input referred noise of 2.8 μV, and consumes 4.5 μW of power. The output of each amplifier is connected to a 10-bit ADC via an adaptive-bias buffer and transmission gate whose transparency is set by the control logic. The control logic timeshares the ADC by multiplexing through one of five preset patterns of 32 on-chip signals. The digitized waveforms are then broadcasted wirelessly using a 900 MHz FSK transmitter. The entire chip consumes 7.2 mW of power during operation

Low-Power Circuits for Brain–Machine Interfaces

This paper presents work on ultra-low-power circuits for brain–machine interfaces with applications for paralysis prosthetics, stroke, Parkinson’s disease, epilepsy, prosthetics for the blind, and experimental neuroscience systems. The circuits include a micropower neural amplifier with adaptive power biasing for use in multi-electrode arrays; an analog linear decoding and learning architecture for data compression; low-power radio-frequency (RF) impedance-modulation circuits for data telemetry that minimize power consumption of implanted systems in the body; a wireless link for efficient power transfer; mixed-signal system integration for efficiency, robustness, and programmability; and circuits for wireless stimulation of neurons with power-conserving sleep modes and awake modes. Experimental results from chips that have stimulated and recorded from neurons in the zebra finch brain and results from RF power-link, RF data-link, electrode- recording and electrode-stimulating systems are presented. Simulations of analog learning circuits that have successfully decoded prerecorded neural signals from a monkey brain are also presented