Constandinou, TG

Paraskevopoulou, SE

English

Spiral - Imperial College Digital Repository

An Ultra-Low-Power Front-end Neural Interfacewith Automatic Gain for Uncalibrated MonitoringSivylla E. Paraskevopoulou∗† and Timothy G. Constandinou∗†∗Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK†Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UKEmail: {s.paraskevopoulou09,t.constandinou}@imperial.ac.ukAbstract—This paper presents a dynamic front-end towardsachieving unsupervised single-neuron activity monitoring. Byimplementing at the front-end, an automatic gain control thatis optimized for neural signal dynamics, subsequent processingcan be achieved without the need for calibration. The systemuses three amplification stages (low-noise first stage, variable-gain second stage and high-gain third stage), a tuneable high-pass filter, and a feedback loop to tune the variable gain. The cir-cuit has been implemented in a commercially-available 0.18µmCMOS technology with total power consumption between 1.79and 1.95µW . The front-end achieves a variable gain from 52to 86.4 dB with 3 kHz bandwidth and a high-pass filter that istuneable from 100-300 Hz. The input referred noise is 9.66µVwith a total harmonic distortion of under 1%.I. INTRODUCTIONHigh density micro electrode arrays are now commercially-available (eg. Blackrock microsystems, Neuronexus, etc) andtogether with integrated microelectronics are presenting newopportunities for tapping into the nervous system. Such sys-tems are currently able to monitor tens to hundreds of channelsand soon will be extending to thousands [1]. The actionpotentials that are recorded have small amplitude (25µV to1mV ) and a specific frequency range (up to 3 kHz). Commonto all neural interfaces is the front-end amplifier. Key aspectsin the design of a robust neural amplifier are: (1) low-powerconsumption to enable high-channel count and implantability(since any power consumed is ultimately thermally dissipated,it is crucial to avoid heating the tissue); (2) high gain toamplify the signal sufficiently for subsequent signal processingand data conversion; (3) low input referred noise to avoid bury-ing the small amplitude spikes in the amplifier induced noise;(4) good linearity to prevent distortion of the spike features;(5) high-pass filtering to eliminate the Local Field Potentials(signals of much larger amplitude and with frequency rangeup to 300Hz [2]) and (6) capacitative coupling to eliminatethe DC offset drift introduced by the electrode-tissue interface.Various designs have been reported in the literature; somefocusing on high gain [3], some achieving great noise per-formance [2]–[4], others consuming very little power [5],[6], or combining these characteristics. However a feature ofneural signals that is often neglected is the relatively largevariation between spike amplitude that can vary up to 32 dBin magnitude. Therefore, if a recorded signal of amplitudebetween 25µV to 1mV is amplified by a fixed gain stage (forexample 40 dB), the output signal will range between 2.5mVTuneableHigh Pass FilterSTAGE 2Variable GainSTAGE 3High-VoutC5C6Spike Peakand MagnitudeDetectorV to IConverterSTAGE 1VrefAgnd(VDD/2)C4C3VinC1C2Automatic Gain Control FeedbackHPFVGAIbiasFig. 1. Front-end system architecture. Spike peak and magnitude detectordetailed previously in [7].and 100mV . This renders the design of subsequent processingtopologies challenging in order to accommodate signals of allamplitudes.In this paper, we present a variable gain neural amplifierwith automatic gain control, ultra-low power consumption, lowinput referred noise, and tuneable high-pass cut-off frequency.The paper is organized as follows: Section II outlines thesystem architecture and describes the circuit implementation,Section III presents the simulated results, and Section IVdiscusses the system performance.II. SYSTEM ARCHITECTURE AND IMPLEMENTATIONThe complete system architecture is illustrated in Fig. 1.The first stage is a low-noise neural amplifier, the secondamplification stage has variable gain, and the third stage isa high gain stage. Between the second and third stage, a high-pass filter (HPF) with tuneable cut-off frequency eliminates theLFPs. The circuits has been implemented in a commercially-available 0.18µm 1P4M CMOS technology provided by IBM.A. Pre-amplifierThe pre-amplifier design (see Fig. 1) has been adapted fromthe well-established neural amplifier topology [4]. The input(Vin) and reference bias (Vref ) are capacitively coupled tothe recording and reference electrodes respectively. The mid-band gain is set by the ratio C1/C2 to be 20 dB. The gainof the pre-amplifier is kept to be relatively low, so as notto affect the linearity of the subsequent stage (explained inSection II-B). The first stage high pass cut-off frequency isdetermined by the fixed-value high-resistance pseudoresistors(diode connected pMOS devices) and the input capacitors, andgm1gm2CVinVoutIbias1 Ibias2Fig. 2. Variable gain amplifier architecture.serves to eliminate any DC offset from the input. The low-pass cut-off frequency is determined by the dominant poleof the Operational Transconductance Amplifier (OTA), whichis Gm/CL, where Gm is the transconductance of the OTAand CL the load capacitor. The OTA used is a fully-balancedtopology with the input differential devices biased further inweak inversion than the current mirror devices. This is toreduce the input referred noise according to Eq. 1 [8].vnoise,ota =√[16VT3qgm1·(1 + 3gm2gm1)]·BW (1)where gm1 is the transconductance of the input devices, gm2the transconductance of the current mirror devices, VT thethermal voltage, and q the electron charge.B. Variable Gain AmplifierThe variable gain amplifier (VGA) is required to normal-ize the recorded spikes such that to remove any amplitudevariations. The signal at the input of the VGA has a rangevarying from 500µV to 20mV , whereas the output signalhas a fixed range of 20mV . The VGA is shown in Fig. 2,and it is based on a gm-C filter topology [9]. The gain is setby the ratio gm1/gm2, with the dominant pole at gm2/C.Transistors M1-M2 (the input differential pairs) are biased inthe weak inversion region, and therefore gm1 and gm2 arerelated to the OTA input bias current according the Eq. 2 [10].The gain is therefore set to Ibias1/Ibias2.gm =IDSnVT(2)where IDS the current flowing from source to drain (for apMOS device).To increase the linear range of the VGA, the OTAs arelinearized using source degeneration via symmetric diffusors(devices M3-M4) [11]. For a given bias current, the totalharmonic distortion (THD) is influenced by two factors: theoutput range and the amplifier gain. In order to not surpass aTHD of 1%, the output range of the VGA must be kept to amaximum of 20mV . More specifically, even though THD isonly 0.2% when the gain is set at 1 (input and output range is20mV ), this increases to 1% when the gain is set to 40 (inputrange of 500µV and output 20mV ).In previous work [7], we presented a circuit that detects thespike peak magnitude and converts it into a DC voltage. Thisvoltage is the input of the feedback loop (shown in Fig.4)determining the gain of the VGA. This DC voltage rangesfrom 912.5mV to 1.4V , assuming an overall amplificationof 54 dB (preceding the peak magnitude detection) with thesignals biased about the analogue ground (ie. mid-supply).M1 M2M3M4M5M6 M7 M8M9 M10Vin+Vin+Vin-Vin- VoutVbias IbiasM114/450/0.550/0.5100/0.5 100/0.51/201/20 1/20 1/201/20 1/20Fig. 3. Linearised OTA (with symmetric diffusors) used in the VGA.VoutVbVinVpM1M2M3M5 M6M7M8 M9M10Rs4/44/44/410/10 10/1010/10 10/104/41/20Level shifter V to I converterFig. 4. Feedback loop providing automatic gain control.The level-shifter decreases the DC input voltage to a levelwhere the V-I converter operates linearly. The V-I converter[12] converts the DC voltage into a equivalent current. So, DCvoltage (of 32 dB dynamic range) representing the spike peakamplitude is converted to an equivalent DC current (from 1to 40nA) that biases OTA2 of the VGA (the bias current ofOTA1 is constant).C. Tuneable High Pass FilterThe high pass filter is based on a gm-C topology (shown inFig. 8) with identical OTAs [9]. The transfer function of thefilter is described in Eq. 3. The pole is located at gm ·√1C1C2,where gm is the OTA transconductance. The input transistorsof the OTAs are biased in the weak inversion region, so the gmis proportional to bias current (Ibias) of the OTA (relationshipdescribed in Eq. 2). Hence, the cut-off frequency of the high-pass filter is tuneable and proportional to Ibias. The qualitativefactor Q of the filter is given by the capacitor ratio√C2/C1and is set at 0.5.H(s) =s2C1C2s2C1C2 + sC1gm + gm2(3)D. High-Gain StageThe third stage amplifier is the highest-gain (34 dB) stage,with the gain determined by the ratio of capacitors C5/C6 (seeFig. 1). The pseudoresistors are added to create a high-passfilter with corner frequency at approximately 100mHz (refergmgmC1C2ViVoFig. 5. High-pass filter architecture.Vin+Vin-Ibias/2M1 M2M3M4VoutM5M6M7 M8M9 M10M11 M12M13 M14M154/410/10 10/1040/4 40/4 40/440/440/440/440/440/4 4/44/44/44/4VbiasFig. 6. Stabilised (through cascoding) OTA used in the HPF.to Eq. 4 [8]), in order to filter out any DC offset added by theprevious stages.fL =12πRC6(4)where R is the incremental resistance of the pseudoresistors(larger than 1011Ω [4]).III. SIMULATED RESULTSThe circuits have been simulated using the Cadence Spec-tre (5.1.41ISR3) simulator with foundry supplied BSIM3v3models.A. Performance of the VGAThe variable gain amplifier was tested using a sine wave offrequency 1 kHz and amplitude from 250µV to 10mV . Thisrange was selected given the 20 dB gain of the pre-amplifierand the 25µV to 1mV range of the recorded signal. Resultsof a transient analysis are shown in Fig. 7. This illustrates howthe output is mapped to a fixed 20mV . Any offset introducedwill be filtered-out by the subsequent circuitry.B. Tuneability of the High Pass FilterFig. 8 shows the linear dependence of the filter’s cutofffrequency to the OTA bias current. By selecting bias current(Ibias) from 1 to 15nA, the change in frequency responsechanges is shown. More realistically, the desired high passfrequency for a neural amplifier should vary between 100 and300Hz. Any value larger than that will interfere with the spike915910905900895890885V(mV)925920915910905900895890time(ms)0 25 75 100 12550V(mV)INOUTFig. 7. Operation of the variable gain stage to provide automatic gain.Freq (Hz) -200-175-150-125-100-75-50-25025Y0 (dB)10-2 10-1 100 101 102 103 104 1051nA15nAFig. 8. Spectral response of the high pass filter showing tuneability (forIbias from 1nA to 15nA).spectrum and with any smaller value the LFPs would not befiltered out. To achieve cutoff frequencies of 100Hz, 200Hzand 300Hz, the bias current needed is 2nA, 4nA, and 6nA,respectively.C. System Simulations with Neural SignalsThe datasets used are simulated neural signals sampled at 24kHz1. In these signals the Noise-to-Signal Ratio (NSR) variesbetween 0.05 and 0.4. The noise represents the backgroundcerebral activity picked up by the electrodes. This systematicnoise should have the same absolute value in all recordedsignals, considering the proximity of the recording electrodes.To derive test signals for our amplifier from the originaldata sets, we normalized them to the desired spike amplitudeusing for each amplitude a data set with such NSR that thesystematic noise level would be equal for all test signals (seeTable I). The output of the three-stage amplifier when inputingthese neural signals is shown in Fig. 9.TABLE INEURAL DATA SETS AMPLITUDE AND NOISE-TO-SIGNAL RATIOData set Spike amplitude NSR1 25µV 0.42 50µV 0.23 100µV 0.14 200µV 0.051http://www2.le.ac.uk/departments/engineering/research/bioengineering/neuroengineering-lab/spike-sortingTABLE IITABLE SHOWING SPECIFICATION FOR INDIVIDUAL BUILDING BLOCKS.Pre-amp VGA HPF Stage3 FeedbackGain 20.1 dB 0-31.25 dB -1.15 dB 33.5 dB -Low-pass cut-off frequency 0.1Hz - 100-300Hz 0.1Hz -High-pass cut-off frequency 8.4 kHz 3.8-115 kHz - 3 kHz -Integrated Noise 9.66µV 20-28µV 37µV 32µV -THD 0.1% 1% 0.5% 0.1% -Power consumption 0.72µW 0.15-0.3µW 7.2-21.6nW 0.36µW 0.35-0.56µW0.60.81.01.21.40.60.81.01.21.40.60.81.01.21.40.60.81.01.21.4899.8899.9900900.1900.2899.8899.9900900.1900.2V(mV)V(mV)V(mV)V(mV)V(V)V(V)V(V)V(V)0 25 50 75 100Time(ms)0 25 50 75 100Time(ms)0 25 50 75 100Time(ms)0 25 50 75 100Time(ms)0 25 50 75 100Time(ms)0 25 50 75 100Time(ms)0 25 50 75 100Time(ms)0 25 50 75 100Time(ms)899.8899.9900900.1900.2899.8899.9900900.1900.2(a)(b)(c)(d)Fig. 9. Transient response demonstrating automatic gain control with neuralinput signals of varying amplitudes (shown on left) and front-end output(shown on right). Input signals are: (a) Data set 1 (30µVptp), (b) Data set 2(60µVptp), (c) Data set 3 (125µVptp), and (d) Data set 4 (375µVptp).IV. CONCLUSIONIn this paper we have presented a front-end neural interfacewith tuneable high-pass frequency and automatic gain controlimplemented in a standard 0.18µm CMOS technology. Thecircuit consumes under 1.5µW power consumption, withoutsacrificing noise performance (input referred noise is below10µV ), high gain (more than 80 dB), or bandwidth (100Hz-3 kHz). The specifications of the individual sub-componentswithin the front-end are given in Table II.Table III compares the design presented herein with rel-evant neural (biopotential) amplifiers that provide a variablegain. A common comparison criterion is the Noise EfficiencyFigure (NEF) [8], calculated by Eq. 5, that is a measure ofthe trade-off between effectiveness against noise and currentconsumption. Smaller NEF indicates noise efficiency.NEF = Vni,rms√2Itotπ · q · (2VT )2 ·BW(5)where Vni,rms is the input-referred noise voltage, Itot isthe total amplifier supply current, and BW is the amplifierbandwidth.TABLE IIIPERFORMANCE COMPARISON WITH OTHER PGA/VGAS[13] [14] [15] This workTechnology 0.5µm 0.18µm 0.18µm 0.18µmSupply voltage 3V 1.8V 1.8 V 1.8VPower cons. 50µW 41.4µW 26µW 1.2-1.4µWGain 40-61 dB 52-57 dB 0-40 dB 52-86 dBLow pass freq. 7-416Hz 300Hz † 50Hz 100-300Hz †High pass freq. 10 kHz 10 kHz 900Hz 3 kHzInput-ref. noise 4.8µV 1.61µV 5.6µV 9.66µVNEF 7.75 4.73 5.83 4VGA/PGA PGA VGA VGA VGAVGA/PGA=Variable/programmable gain, †Tuneable cut-off frequencyACKNOWLEDGMENTThis work was supported by the UK Engineering and Phys-ical Sciences Research Council (Grant ref: EP/I000569/1).REFERENCES[1] A. Eftekhar, S. E. Paraskevopoulou, and T. G. Constandinou, “Towardsa Next Generation Neural Interface: Optimizing Power, Bandwidth andData Quality,” Proc. IEEE BioCAS, pp. 122–125, 2010.[2] R. Harrison, “A Versatile Integrated Cricuit for the Acquisition ofBiopotentials,” Proc. IEEE CICC, pp. 115–122, 2007.[3] T. Borghi et al., “A Power-Efficient Analog Integrated Circuit forAmplification and Detection of Neural Signals,” Proc. IEEE EMBS,pp. 4911–4915, 2008.[4] R. Harrison and C. Charles, “A Low-Power Low-Noise CMOS Ampli-fier for Neural Recording Applications,” IEEE Journal of Solid-StateCircuits, vol. 38, no. 6, pp. 958–965, 2003.[5] J. Kim, M. Chae, and W. Liu, “A 220nW Neural Amplifier for Multi-Channel Neural Recording Systems,” Proc. IEEE ISCAS, pp. 1257–1260,2009.[6] T. Horiuchi et al., “A Low-Power CMOS Neural Amplifier with Am-plitude Measurements for Spike Sorting,” Proc. IEEE ISCAS, vol. 4,pp. 29–32, 2004.[7] S. E. Paraskevopoulou and T. G. Constandinou, “A sub-1µV NeuralSpike Detection and Spike-Count Rate Encoding Circuit,” Proc. IEEEBioCAS, 2011.[8] R. Harrison, “The design of integrated circuits to observe brain activity,”Proc. IEEE, vol. 96, no. 7, pp. 1203–1216, 2008.[9] R. Geiger and E. Sánchez-Sinencio, “Active Filter Design Using Op-erational Transconductance Amplifiers: A Tutorial,” IEEE Circuits andDevices Magazine, vol. 1, pp. 20–32, 1985.[10] W. Sansen, Analog Design Essentials. Springer, 2006.[11] P. Furth and A. Andreou, “Linearised differential transconductor insunthreshold CMOS,” IET Elec. Lett., vol. 31, no. 7, pp. 545–546, 1995.[12] C. Azcona et al., “Highly-linear rail-to-rail 1.2V-0.18m CMOS V-Iconverter,” IET Elec. Lett., vol. 47, no. 18, pp. 1018–1019, 2011.[13] G. Perlin, A. Sodagar, and K. Wise, “A Neural Amplifier with Pro-grammable Gain and Tunable Bandwidth,” Proc. IEEE EMBS, pp. 3154–3157, 2008.[14] H. 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An Ultra-Low-Power Front-End Neural Interface with Automatic Gain for Uncalibrated Monitoring

An Ultra-Low-Power Front-End Neural Interface with Automatic Gain for Uncalibrated Monitoring

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