Force feedback linearization for higher-order electromechanical sigma-delta modulators.

Abstract A higher-order electromechanical sigma–delta modulator can greatly improve the signal-to-noise ratio compared with a second-order loop that only uses the sensing element as a loop filter. However, the electrostatic force feedback on the proof mass is inherently nonlinear, which will produce harmonics in the output spectrum and limits the total signal-to-noise and distortion ratio. High performance inertial sensors, which use sigma–delta modulators as a closed-loop control system, have strict requirements on the output signal distortion. In this paper, nonlinear effects from the force feedback and pick-off circuits are analysed and a strategy for force feedback linearization is put forward which can considerably improve the signal-to-noise and distortion ratio. A PCB prototype of a fifth-order electromechanical modulator with a bulk micromachined accelerometer was used to demonstrate the concept

A closed-loop digitally controlled MEMS gyroscope with unconstrained Sigma-Delta force-feedback

In this paper, we describe the system architecture and prototype measurements of a MEMS gyroscope system with a resolution of 0.025 degrees/s/root Hz. The architecture makes extensive use of control loops, which are mostly in the digital domain. For the primary mode both the amplitude and the resonance frequency are tracked and controlled. The secondary mode readout is based on unconstrained Sigma Delta force-feedback, which does not require a compensation filter in the loop and thus allows more beneficial quantization noise shaping than prior designs of the same order. Due to the force-feedback, the gyroscope has ample dynamic range to correct the quadrature error in the digital domain. The largely digital setup also gives a lot of flexibility in characterization and testing, where system identification techniques have been used to characterize the sensors. This way, a parasitic direct electrical coupling between actuation and readout of the mass-spring systems was estimated and corrected in the digital domain. Special care is also given to the capacitive readout circuit, which operates in continuous time

A sigma-delta interface built-in self-test and calibration for microelectromechanical system accelerometer's utilizing interpolation method

This work presents the capacitive micromechanical accelerometer with a completely differential high-order switched capacitor sigma-delta modulator interface. Such modulation interface circuit generates one-bit output data using a third sigma-delta modulator low-noise front-end, doing away with the requirement for a second enhanced converter of resolution to encode the feedback route analog signal. A capacitive micromechanical sensor unit with just a greater quality factor has been specifically employed to give greater resolution. The closed-loop and electrical correction control are used to dampen the high-Q values to get the system's stability with high-order. This microelectromechanical system (MEMS) capacitive accelerometer was calibrated using a lookup table and Akima interpolation to find manufacturing flaws by recalculating voltage levels for the test electrodes. To determine the proper electrode voltages for fault compensation, COMSOL software simulates a number of defects upon that spring as well as the fingers of the sensor system. When it comes time for the feedback phase of a proof mass displacement correction, these values are subsequently placed in the lookup table

Integrated system for a high resolution MEMS accelerometer

Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores (Major Telecomunicações). Faculdade de Engenharia. Universidade do Porto. 201

Capacitive Microaccelerometers And Fabrication Methods

Disclosed are moveable microstructures comprising in-plane capacitive microaccelerometers, with submicro-gravity resolution (17 pF/g). Themicrostructures are fabricated in thick(> 100 µm) siliconon-insulator (SOI) substrates or silicon substrates using a two-mask fully-dry release process that provides large seismic mass (> 10 milli-g), reduced capacitive gaps, and reduced in-plane stiffness. Fabricated devices may be interfaced to a high resolution switched-capacitor CMOS IC that eliminates the need for area-consuming reference capacitors. The measured sensitivity is 83 mV/mg (17 pF/g) and the output noise floor is -91 dBm/Hz at 10 Hz (corresponding to an acceleration resolution of 170 ng/√Hz). The IC consumes 6 mW power and measures 0.65 mm2 core area.Georgia Tech Research Corporatio

Multi-Physics Simulation Platform and Multi-Layer Metal Technology for CMOS-MEMS Accelerometer with Gold Proof Mass

This chapter describes technical features and solutions to realize a highly sensitive CMOS-MEMS accelerometer with gold proof mass. The multi-physics simulation platform for designing the CMOS-MEMS device has been developed to understand simultaneously both mechanical and electrical behaviors of MEMS stacked on LSI. MEMS accelerometer fabrication process is established by the multi-layer metal technology, which consists of the gold electroplating and the photo-sensitive polyimide film. The proposed MEMS accelerometers are fabricated and evaluated to verify the effectiveness of the proposed techniques regarding sub-1G MEMS and arrayed MEMS devices. The experimental results show that the Brownian noise of the sub-1G MEMS accelerometer can achieve 780 nG/(Hz)1/2 and the arrayed MEMS accelerometer has a wide detection, ranging from 1.0 to 20 G. Moreover, using the developed simulation platform, we demonstrate the proposed capacitive CMOS-MEMS accelerometer implemented by the multi-layer metal technology. In conclusion, it is confirmed that the multi-physics simulation platform and the multi-layer metal technology for the CMOS-MEMS device have a potential to realize a nano-gravity sensing technology

A Low-Power Interface for Capacitive Sensors With PWM Output and Intrinsic Low Pass Characteristic

A compact, low power interface for capacitive sensors, is described. The output signal is a pulse width modulated (PWM) signal, where the pulse duration is linearly proportional to the sensor differential capacitance. The original conversion approach consists in stimulating the sensor capacitor with a triangular-like voltage waveform in order to obtain a square-like current waveform, which is subsequently demodulated and integrated over a clock period. The charge obtained in this way is then converted into the output pulse duration by an approach that includes an intrinsic tunable low pass function. The main non idealities are thoroughly investigated in order to provide useful design indications and evaluate the actual potentialities of the proposed circuit. The theoretical predictions are compared with experimental results obtained with a prototype, designed and fabricated using 0.32 mu M CMOS devices from the BCD6s process of STMicroelectroncs. The prototype occupies a total area of 1025 x 515 mm(2) and is marked by a power consuption of 84 mu W. The input capacitance range is 0-256 fF, with a resolution of 0.8 fF and a temperature sensitivity of 300 ppm/degrees C

Analog baseband circuits for sensor systems

This thesis is composed of six publications and an overview of the research topic, which also summarizes the work. The research presented in this thesis focuses on research into analog baseband circuits for sensor systems. The research is divided into three different topics: the integration of analog baseband circuits into a radio receiver for sensor applications; the integration of an ΔΣ modulator A/D converter into a GSM/WCDMA radio receiver for mobile phones, and the integration of algorithmic A/D converters for a capacitive micro-accelerometer interface. All the circuits are implemented using deep sub-micron CMOS technologies. The work summarizes the design of different blocks for sensor systems. The research into integrated analog baseband circuits for a radio receiver focuses on a circuit structures with a very low power dissipation and that can be implemented using only standard CMOS technologies. The research into integrated ΔΣ modulator A/D converter design for a GSM/WCDMA radio receiver for mobile phones focuses on the implications for analog circuit design emerging from using a very deep sub-micron CMOS process. Finally, in the research into algorithmic A/D converters for a capacitive microaccelerometer interface, new ways of achieving a good performance with low power dissipation, while also minimizing the silicon area of the integrated A/D converter are introduced