Edge-Fault Tolerance of Hypercube-like Networks

This paper considers a kind of generalized measure $\lambda_s^{(h)}$ of fault tolerance in a hypercube-like graph $G_n$ which contain several well-known interconnection networks such as hypercubes, varietal hypercubes, twisted cubes, crossed cubes and M\"obius cubes, and proves $\lambda_s^{(h)}(G_n)= 2^h(n-h)$ for any $h$ with $0\leqslant h\leqslant n-1$ by the induction on $n$ and a new technique. This result shows that at least $2^h(n-h)$ edges of $G_n$ have to be removed to get a disconnected graph that contains no vertices of degree less than $h$. Compared with previous results, this result enhances fault-tolerant ability of the above-mentioned networks theoretically

Epic Fail: Emulators Can Tolerate Polynomially Many Edge Faults for Free

A t-emulator of a graph G is a graph H that approximates its pairwise shortest path distances up to multiplicative t error. We study fault tolerant t-emulators, under the model recently introduced by Bodwin, Dinitz, and Nazari [ITCS 2022] for vertex failures. In this paper we consider the version for edge failures, and show that they exhibit surprisingly different behavior. In particular, our main result is that, for (2k-1)-emulators with k odd, we can tolerate a polynomial number of edge faults for free. For example: for any n-node input graph, we construct a 5-emulator (k = 3) on O(n^{4/3}) edges that is robust to f = O(n^{2/9}) edge faults. It is well known that ?(n^{4/3}) edges are necessary even if the 5-emulator does not need to tolerate any faults. Thus we pay no extra cost in the size to gain this fault tolerance. We leave open the precise range of free fault tolerance for odd k, and whether a similar phenomenon can be proved for even k

Fault tolerant architectures for integrated aircraft electronics systems, task 2

The architectural basis for an advanced fault tolerant on-board computer to succeed the current generation of fault tolerant computers is examined. The network error tolerant system architecture is studied with particular attention to intercluster configurations and communication protocols, and to refined reliability estimates. The diagnosis of faults, so that appropriate choices for reconfiguration can be made is discussed. The analysis relates particularly to the recognition of transient faults in a system with tasks at many levels of priority. The demand driven data-flow architecture, which appears to have possible application in fault tolerant systems is described and work investigating the feasibility of automatic generation of aircraft flight control programs from abstract specifications is reported

Assessing Asymmetric Fault-Tolerant Software

The most popular forms of fault tolerance against design faults use "asymmetric" architectures in which a "primary" part performs the computation and a "secondary" part is in charge of detecting errors and performing some kind of error processing and recovery. In contrast, the most studied forms of software fault tolerance are "symmetric" ones, e.g. N-version programming. The latter are often controversial, the former are not. We discuss how to assess the dependability gains achieved by these methods. Substantial difficulties have been shown to exist for symmetric schemes, but we show that the same difficulties affect asymmetric schemes. Indeed, the latter present somewhat subtler problems. In both cases, to predict the dependability of the fault-tolerant system it is not enough to know the dependability of the individual components. We extend to asymmetric architectures the style of probabilistic modeling that has been useful for describing the dependability of "symmetric" architectures, to highlight factors that complicate the assessment. In the light of these models, we finally discuss fault injection approaches to estimating coverage factors. We highlight the limits of what can be predicted and some useful research directions towards clarifying and extending the range of situations in which estimates of coverage of fault tolerance mechanisms can be trusted

Fault-Tolerant Spanners against Bounded-Degree Edge Failures: Linearly More Faults, Almost For Free

We study a new and stronger notion of fault-tolerant graph structures whose size bounds depend on the degree of the failing edge set, rather than the total number of faults. For a subset of faulty edges $F \subseteq G$, the faulty-degree $\deg(F)$ is the largest number of faults in $F$ incident to any given vertex. We design new fault-tolerant structures with size comparable to previous constructions, but which tolerate every fault set of small faulty-degree $\deg(F)$, rather than only fault sets of small size $|F|$. Our main results are: - New FT-Certificates: For every $n$-vertex graph $G$ and degree threshold $f$, one can compute a connectivity certificate $H \subseteq G$ with $|E(H)| = \widetilde{O}(fn)$ edges that has the following guarantee: for any edge set $F$ with faulty-degree $\deg(F)\leq f$ and every vertex pair $u,v$, it holds that $u$ and $v$ are connected in $H \setminus F$ iff they are connected in $G \setminus F$. This bound on $|E(H)|$ is nearly tight. Since our certificates handle some fault sets of size up to $|F|=O(fn)$, prior work did not imply any nontrivial upper bound for this problem, even when $f=1$. - New FT-Spanners: We show that every $n$-vertex graph $G$ admits a $(2k-1)$-spanner $H$ with $|E(H)| = O_k(f^{1-1/k} n^{1+1/k})$ edges, which tolerates any fault set $F$ of faulty-degree at most $f$. This bound on $|E(H)|$ optimal up to its hidden dependence on $k$, and it is close to the bound of $O_k(|F|^{1/2} n^{1+1/k} + |F|n)$ that is known for the case where the total number of faults is $|F|$ [Bodwin, Dinitz, Robelle SODA '22]. Our proof of this theorem is non-constructive, but by following a proof strategy of Dinitz and Robelle [PODC '20], we show that the runtime can be made polynomial by paying an additional $\text{polylog } n$ factor in spanner size

Vertex Fault-Tolerant Emulators

A $k$-spanner of a graph $G$ is a sparse subgraph that preserves its shortest path distances up to a multiplicative stretch factor of $k$, and a $k$-emulator is similar but not required to be a subgraph of $G$. A classic theorem by Thorup and Zwick [JACM '05] shows that, despite the extra flexibility available to emulators, the size/stretch tradeoffs for spanners and emulators are equivalent. Our main result is that this equivalence in tradeoffs no longer holds in the commonly-studied setting of graphs with vertex failures. That is: we introduce a natural definition of vertex fault-tolerant emulators, and then we show a three-way tradeoff between size, stretch, and fault-tolerance for these emulators that polynomially surpasses the tradeoff known to be optimal for spanners. We complement our emulator upper bound with a lower bound construction that is essentially tight (within $\log n$ factors of the upper bound) when the stretch is $2k-1$ and $k$ is either a fixed odd integer or $2$. We also show constructions of fault-tolerant emulators with additive error, demonstrating that these also enjoy significantly improved tradeoffs over those available for fault-tolerant additive spanners.Comment: To appear in ITCS 202

Software reliability through fault-avoidance and fault-tolerance

The use of back-to-back, or comparison, testing for regression test or porting is examined. The efficiency and the cost of the strategy is compared with manual and table-driven single version testing. Some of the key parameters that influence the efficiency and the cost of the approach are the failure identification effort during single version program testing, the extent of implemented changes, the nature of the regression test data (e.g., random), and the nature of the inter-version failure correlation and fault-masking. The advantages and disadvantages of the technique are discussed, together with some suggestions concerning its practical use

Fault tolerance of stabilizer channels

Stabilizer channels are stabilizer circuits that implement logical operations while mapping from an input stabilizer code to an output stabilizer code. They are widely used to implement fault tolerant error correction and logical operations in stabilizer codes such as surface codes and LDPC codes, and more broadly in subsystem, Floquet and space-time codes. We introduce a rigorous and general formalism to analyze the fault tolerance properties of any stabilizer channel under a broad class of noise models. This includes rigorous but easy-to-work-with definitions and algorithms for the fault distance and hook faults for stabilizer channels. The generalized notion of hook faults which we introduce, defined with respect to an arbitrary subset of a circuit's faults rather than a fixed phenomenological noise model, can be leveraged for fault-tolerant circuit design. Additionally, we establish necessary conditions such that channel composition preserves the fault distance. We apply our framework to design and analyze fault tolerant stabilizer channels for surface codes, revealing novel aspects of fault tolerant circuits.Comment: 28 pages, 234 figures v2 includes an expanded treatment of generalized hook fault

Software reliability through fault-avoidance and fault-tolerance

Strategies and tools for the testing, risk assessment and risk control of dependable software-based systems were developed. Part of this project consists of studies to enable the transfer of technology to industry, for example the risk management techniques for safety-concious systems. Theoretical investigations of Boolean and Relational Operator (BRO) testing strategy were conducted for condition-based testing. The Basic Graph Generation and Analysis tool (BGG) was extended to fully incorporate several variants of the BRO metric. Single- and multi-phase risk, coverage and time-based models are being developed to provide additional theoretical and empirical basis for estimation of the reliability and availability of large, highly dependable software. A model for software process and risk management was developed. The use of cause-effect graphing for software specification and validation was investigated. Lastly, advanced software fault-tolerance models were studied to provide alternatives and improvements in situations where simple software fault-tolerance strategies break down