A Study on the Effect of Bond Stress and Process Temperature on Palladium Coated Silver Wire Bonds on Aluminum Metallization

In the past ten years, the increasing price of gold has motivated the wire bonding industry to look for alternative bonding wire materials in the field of microelectronics packaging. A new candidate wire to replace gold is palladium coated silver wire. In this thesis, the effect of the two specific process parameters “bond stress” and “process temperature” on the ball bonds made with the new candidate wire are investigated. Using 20 μm diameter wire and various level-combinations of these process parameter, ball bonds are produced according to a special accelerated optimization method to result in a target diameter of 46 ± 0.5 μm and target height of 16 ± 0.5 μm. Three different levels are used for each of the specific process parameters. After pre-selecting a few process parameters, the accelerated method determines the levels for the process parameters “impact force” and “electric flame-off current” with a 2×2 design of experiments. Then, the ultrasound parameter is maximized up to a level where a pre-selected ultrasonic deformation occurs to the bonds, maintaining the target bond diameter and height. The bond quality is measured by measuring the shear strength of the bonds. The results show that • the bond geometry is not affected by the bond stress, • the optimized specific process parameters vary by less than ~0.5 % when bond stress values are varied from 60 to 100 MPa, • the variations in optimized parameters are larger than ~3.0 % when the BT is changed from 100 to 200 ºC, • ball bonds achieve acceptable shear strength (> 120 MPa) when the values for both, bond stress and bond temperature, are high, • ultrasound level and shear stress interact, the higher shear stress the lower the ultrasound level required. An average shear strength of ~120 MPa is achieved with 11.4 % ultrasound, 100 MPa bond stress, and 200 ºC bond process temperature. In summary, a robust methodology is presented in this thesis to efficiently optimize the ball bonding process as demonstrated with the new candidate wire has a bondability similar to that of gold wire with only minor adjustment in the bonding process needed

Materials for high-density electronic packaging and interconnection

Electronic packaging and interconnections are the elements that today limit the ultimate performance of advanced electronic systems. Materials in use today and those becoming available are critically examined to ascertain what actions are needed for U.S. industry to compete favorably in the world market for advanced electronics. Materials and processes are discussed in terms of the final properties achievable and systems design compatibility. Weak points in the domestic industrial capability, including technical, industrial philosophy, and political, are identified. Recommendations are presented for actions that could help U.S. industry regain its former leadership position in advanced semiconductor systems production

A Digital Manufacturing Process For Three-Dimensional Electronics

Additive manufacturing (AM) offers the ability to produce devices with a degree of three-dimensional complexity and mass customisation previously unachievable with subtractive and formative approaches. These benefits have not transitioned into the production of commercial electronics that still rely on planar, template-driven manufacturing, which prevents them from being tailored to the end user or exploiting conformal circuitry for miniaturisation. Research into the AM fabrication of 3D electronics has been demonstrated; however, because of material restrictions, the durability and electrical conductivity of such devices was often limited. This thesis presents a novel manufacturing approach that hybridises the AM of polyetherimide (PEI) with chemical modification and selective light-based synthesis of silver nanoparticles to produce 3D electronic systems. The resulting nanoparticles act as a seed site for the electroless deposition of copper. The use of high-performance materials for both the conductive and dielectric elements created devices with the performance required for real-world applications. For printing PEI, a low-cost fused filament fabrication (FFF); also known as fused deposition modelling (FDM), printer with a unique inverted design was developed. The orientation of the printer traps hot air within a heated build environment that is open on its underside allowing the print head to deposit the polymer while keeping the sensitive components outside. The maximum achievable temperature was 120 °C and was found to reduce the degree of warping and the ultimate tensile strength of printed parts. The dimensional accuracy was, on average, within 0.05 mm of a benchmark printer and fine control over the layer thickness led to the discovery of flexible substrates that can be directly integrated into rigid parts. Chemical modification of the printed PEI was used to embed ionic silver into the polymer chain, sensitising it to patterning with a 405 nm laser. The rig used for patterning was a re-purposed vat-photopolymerisation printer that uses a galvanometer to guide the beam that is focused to a spot size of 155 µm at the focal plane. The positioning of the laser spot was controlled with an open-sourced version of the printers slicing software. The optimal laser patterning parameters were experimentally validated and a link between area-related energy density and the quality of the copper deposition was found. In tests where samples were exposed to more than 2.55 J/cm^2, degradation of the polymer was experienced which produced blistering and delamination of the copper. Less than 2.34 J/cm^2 also had negative effect and resulted in incomplete coverage of the patterned area. The minimum feature resolution produced by the patterning setup was 301 µm; however, tests with a photomask demonstrated features an order of magnitude smaller. The non-contact approach was also used to produce conformal patterns over sloped and curved surfaces. Characterisation of the copper deposits found an average thickness of 559 nm and a conductivity of 3.81 × 107 S/m. Tape peel and bend fatigue testing showed that the copper was ductile and adhered well to the PEI, with flexible electronic samples demonstrating over 50,000 cycles at a minimum bend radius of 6.59 mm without failure. Additionally, the PEI and copper combination was shown to survive a solder reflow with peak temperatures of 249°C. Using a robotic pick and place system a test board was automatically populated with surface mount components as small as 0201 resistors which were affixed using high-temperature, Type-V Tin-Silver-Copper solder paste. Finally, to prove the process a range of functional demonstrators were built and evaluated. These included a functional timer circuit, inductive wireless power coils compatible with two existing standards, a cylindrical RF antenna capable of operating at several frequencies below 10 GHz, flexible positional sensors, and multi-mode shape memory alloy actuators

Electronic systems for intelligent particle tracking in the High Energy Physics field

This Ph.D thesis describes the development of a novel readout ASIC for hybrid pixel detector with intelligent particle tracking capabilities in High Energy Physics (HEP) application, called Macro Pixel ASIC (MPA). The concept of intelligent tracking is introduced for the upgrade of the particle tracking system of the Compact Muon Solenoid (CMS) experiment of the Large Hadron Collider (LHC) at CERN: this detector must be capable of selecting at front--end level the interesting particle and of providing them continuously to the back-end. This new functionality is required to cope with the improved performances of the LHC when, in about ten years' time, a major upgrade will lead to the High Luminosity scenario (HL-LHC). The high complexity of the digital logic for particle selection and the very low power requirement of 95% in particle selection and a data reduction from 200 Tb/s/cm2 to 1 Tb/s/cm2. A prototype, called MPA-Light, has been designed, produced and tested. According to the measurements, the prototype respects all the specications. The same device has been used for multi-chip assembly with a pixelated sensor. The assembly characterization with radioactive sources conrms the result obtained on the bare chip

Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications

Im Rahmen der vorliegenden Dissertation zum Thema „Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications“ wurde auf Basis einer 130 nm SiGe BiCMOS Technologie ein Through-Silicon Via (TSV) Technologiemodul zur Herstellung elektrischer Durchkontaktierungen für die Anwendung im Millimeterwellen und Sub-THz Frequenzbereich entwickelt. TSVs wurden mittels elektromagnetischer Simulationen modelliert und in Bezug auf ihre elektrischen Eigenschaften bis in den sub-THz Bereich bis zu 300 GHz optimiert. Es wurden die Wechselwirkungen zwischen Modellierung, Fertigungstechnologie und den elektrischen Eigenschaften untersucht. Besonderes Augenmerk wurde auf die technologischen Einflussfaktoren gelegt. Daraus schlussfolgernd wurde das TSV Technologiemodul entwickelt und in eine SiGe BiCMOS Technologie integriert. Hierzu wurde eine Via-Middle Integration gewählt, welche eine Freilegung der TSVs von der Wafer Rückseite erfordert. Durch die geringe Waferdicke von ca. 75 μm wird einen Carrier Wafer Handling Prozess verwendet. Dieser Prozess wurde unter der Randbedingung entwickelt, dass eine nachfolgende Bearbeitung der Wafer innerhalb der BiCMOS Pilotlinie erfolgen kann. Die Rückseitenbearbeitung zielt darauf ab, einen Redistribution Layer auf der Rückseite der BiCMOS Wafer zu realisieren. Hierzu wurde ein Prozess entwickelt, um gleichzeitig verschiedene TSV Strukturen mit variablen Geometrien zu realisieren und damit eine hohe TSV Design Flexibilität zu gewährleisten. Die TSV Strukturen wurden von DC bis über 300 GHz charakterisiert und die elektrischen Eigenschaften extrahiert. Dabei wurde gezeigt, dass TSV Verbindungen mit sehr geringer Dämpfung <1 dB bis 300 GHz realisierbar sind und somit ausgezeichnete Hochfrequenzeigenschaften aufweisen. Zuletzt wurden vielfältige Anwendungen wie das Grounding von Hochfrequenzschaltkreisen, Interposer mit Waveguides und 300 GHz Antennen dargestellt. Das Potential für Millimeterwellen Packaging und 3D Integration wurde evaluiert. TSV Technologien sind heutzutage in vielen Anwendungen z.B. im Bereich der Systemintegration von Digitalschaltkreisen und der Spannungsversorgung von integrierten Schaltkreisen etabliert. Im Rahmen dieser Arbeit wurde der Einsatz von TSVs für Millimeterwellen und dem sub-THz Frequenzbereich untersucht und die Anwendung für den sub-THz Bereich bis 300 GHz demonstriert. Dadurch werden neue Möglichkeiten der Systemintegration und des Packaging von Höchstfrequenzsystemen geschaffen.:Bibliographische Beschreibung List of symbols and abbreviations Acknowledgement 1. Introduction 2. FEM Modeling of BiCMOS & Interposer Through-Silicon Vias 3. Fabrication of BiCMOS & Silicon Interposer with TSVs 4. Characterization of BiCMOS Embedded Through-Silicon Vias 5. Applications 6. Conclusion and Future Work 7. Appendix 8. Publications & Patents 9. Bibliography 10. List of Figures and Table

High-frequency characterization of embedded components in printed circuit boards

The embedding of electronic components is a three-dimensional packaging technology, where chips are placed inside of the printed circuit board instead of on top. The advantage of this technology is the reduced electronic interconnection length between components. The shorter this connection, the faster the signal transmission can occur. Different high-frequency aspects of chip embedding are investigated within this dissertation: interconnections to the embedded chip, crosstalk between signals on the chip and on the board, and interconnections running on top of or underneath embedded components. The high-frequency behavior of tracks running near embedded components is described using a broadband model for multilayer microstrip transmission lines. The proposed model can be used to predict the characteristic impedance and the loss of the lines. The model is based on two similar approximations that reduce the multilayer substrate to an equivalent single-layer structure. The per-unit-length shunt impedance parameters are derived from the complex effective dielectric constant, which is obtained using a variational method. A complex image approach results in the calculation of a frequency-dependent effective height that can be used to determine the per-unit-length resistance and inductance. A deliberate choice was made for a simple but accurate model that could easily be implemented in current high-frequency circuit simulators. Next to quasi-static electromagnetic simulations, a dedicated test vehicle that allows for the direct extraction of the propagation constant of these multilayer microstrips is manufactured and used to verify the model. The verification of the model using simulation and measurements shows that the proposed model slightly overestimates the loss of the measured multilayer microstrips, but is more accurate than the simulations in predicting the characteristic impedance

NASA Tech Briefs, November 1993

Topics covered: Advanced Manufacturing; Electronic Components and Circuits; Electronic Systems; Physical Sciences; Materials; Computer Programs; Mechanics; Machinery; Fabrication Technology; Mathematics and Information Sciences; Life Sciences