On-Line Dependability Enhancement of Multiprocessor SoCs by Resource Management

This paper describes a new approach towards dependable design of homogeneous multi-processor SoCs in an example satellite-navigation application. First, the NoC dependability is functionally verified via embedded software. Then the Xentium processor tiles are periodically verified via on-line self-testing techniques, by using a new IIP Dependability Manager. Based on the Dependability Manager results, faulty tiles are electronically excluded and replaced by fault-free spare tiles via on-line resource management. This integrated approach enables fast electronic fault detection/diagnosis and repair, and hence a high system availability. The dependability application runs in parallel with the actual application, resulting in a very dependable system. All parts have been verified by simulation

Testing for delay defects utilizing test data compression techniques

textAs technology shrinks new types of defects are being discovered and new fault models are being created for those defects. Transition delay and path delay fault models are two such models that have been created, but they still fall short in that they are unable to obtain a high test coverage of smaller delay defects; these defects can cause functional behavior to fail and also indicate potential reliability issues. The first part of this dissertation addresses these problems by presenting an enhanced timing-based delay fault testing technique that incorporates the use of standard delay ATPG, along with timing information gathered from standard static timing analysis. Utilizing delay fault patterns typically increases the test data volume by 3-5X when compared to stuck-at patterns. Combined with the increase in test data volume associated with the increase in gate count that typically accompanies the miniaturization of technology, this adds up to a very large increase in test data volume that directly affect test time and thus the manufacturing cost. The second part of this dissertation presents a technique for improving test compression and reducing test data volume by using multiple expansion ratios while determining the configuration of the scan chains for each of the expansion ratios using a dependency analysis procedure that accounts for structural dependencies as well as free variable dependencies to improve the probability of detecting faults. Finally, this dissertation addresses the problem of unknown values (X’s) in the output response data corrupting the data and degrading the performance of the output response compactor and thus the overall amount of test compression. Four techniques are presented that focus on handling response data with large percentages of X’s. The first uses X-canceling MISR architecture that is based on deterministically observing scan cells, and the second is a hybrid approach that combines a simple X-masking scheme with the X-canceling MISR for further gains in test compression. The third and fourth techniques revolve around reiterative LFSR X-masking, which take advantage of LFSR-encoded masks that can be reused for multiple scan slices in novel ways.Electrical and Computer Engineerin

REDUCING POWER DURING MANUFACTURING TEST USING DIFFERENT ARCHITECTURES

Power during manufacturing test can be several times higher than power consumption in functional mode. Excessive power during test can cause IR drop, over-heating, and early aging of the chips. In this dissertation, three different architectures have been introduced to reduce test power in general cases as well as in certain scenarios, including field test. In the first architecture, scan chains are divided into several segments. Every segment needs a control bit to enable capture in a segment when new faults are detectable on that segment for that pattern. Otherwise, the segment should be disabled to reduce capture power. We group the control bits together into one or more control chains. To address the extra pin(s) required to shift data into the control chain(s) and significant post processing in the first architecture, we explored a second architecture. The second architecture stitches the control bits into the chains they control as EECBs (embedded enable capture bits) in between the segments. This allows an ATPG software tool to automatically generate the appropriate EECB values for each pattern to maintain the fault coverage. This also works in the presence of an on-chip decompressor. The last architecture focuses primarily on the self-test of a device in a 3D stacked IC when an existing FPGA in the stack can be programmed as a tester. We show that the energy expended during test is significantly less than would be required using low power patterns fed by an on-chip decompressor for the same very short scan chains

Infrastructures and Algorithms for Testable and Dependable Systems-on-a-Chip

Every new node of semiconductor technologies provides further miniaturization and higher performances, increasing the number of advanced functions that electronic products can offer. Silicon area is now so cheap that industries can integrate in a single chip usually referred to as System-on-Chip (SoC), all the components and functions that historically were placed on a hardware board. Although adding such advanced functionality can benefit users, the manufacturing process is becoming finer and denser, making chips more susceptible to defects. Today’s very deep-submicron semiconductor technologies (0.13 micron and below) have reached susceptibility levels that put conventional semiconductor manufacturing at an impasse. Being able to rapidly develop, manufacture, test, diagnose and verify such complex new chips and products is crucial for the continued success of our economy at-large. This trend is expected to continue at least for the next ten years making possible the design and production of 100 million transistor chips. To speed up the research, the National Technology Roadmap for Semiconductors identified in 1997 a number of major hurdles to be overcome. Some of these hurdles are related to test and dependability. Test is one of the most critical tasks in the semiconductor production process where Integrated Circuits (ICs) are tested several times starting from the wafer probing to the end of production test. Test is not only necessary to assure fault free devices but it also plays a key role in analyzing defects in the manufacturing process. This last point has high relevance since increasing time-to-market pressure on semiconductor fabrication often forces foundries to start volume production on a given semiconductor technology node before reaching the defect densities, and hence yield levels, traditionally obtained at that stage. The feedback derived from test is the only way to analyze and isolate many of the defects in today’s processes and to increase process’s yield. With the increasing need of high quality electronic products, at each new physical assembly level, such as board and system assembly, test is used for debugging, diagnosing and repairing the sub-assemblies in their new environment. Similarly, the increasing reliability, availability and serviceability requirements, lead the users of high-end products performing periodic tests in the field throughout the full life cycle. To allow advancements in each one of the above scaling trends, fundamental changes are expected to emerge in different Integrated Circuits (ICs) realization disciplines such as IC design, packaging and silicon process. These changes have a direct impact on test methods, tools and equipment. Conventional test equipment and methodologies will be inadequate to assure high quality levels. On chip specialized block dedicated to test, usually referred to as Infrastructure IP (Intellectual Property), need to be developed and included in the new complex designs to assure that new chips will be adequately tested, diagnosed, measured, debugged and even sometimes repaired. In this thesis, some of the scaling trends in designing new complex SoCs will be analyzed one at a time, observing their implications on test and identifying the key hurdles/challenges to be addressed. The goal of the remaining of the thesis is the presentation of possible solutions. It is not sufficient to address just one of the challenges; all must be met at the same time to fulfill the market requirements

Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices

Low-cost test and tuning methods for difficult-to-measure specifications are presented in this research from the following perspectives: 1)"Safe" test and self-tuning for power converters: To avoid the risk of device under test (DUT) damage during conventional load/line regulation measurement on power converter, a "safe" alternate test structure is developed where the power converter (boost/buck converter) is placed in a different mode of operation during alternative test (light switching load) as opposed to standard test (heavy switching load) to prevent damage to the DUT during manufacturing test. Based on the alternative test structure, self-tuning methods for both boost and buck converters are also developed in this thesis. In addition, to make these test structures suitable for on-chip built-in self-test (BIST) application, a special sensing circuit has been designed and implemented. Stability analysis filters and appropriate models are also implemented to predict the DUT’s electrical stability condition during test and to further predict the values of tuning knobs needed for the tuning process. 2) High bandwidth RF signal generation: Up-convertion has been widely used in high frequency RF signal generation but mixer nonlinearity results in signal distortion that is difficult to eliminate with such methods. To address this problem, a framework for low-cost high-fidelity wideband RF signal generation is developed in this thesis. Depending on the band-limited target waveform, the input data for two interleaved DACs (digital-to-analog converters) system is optimized by a matrix-model-based algorithm in such a way that it minimizes the distortion between one of its image replicas in the frequency domain and the target RF waveform within a specified signal bandwidth. The approach is used to demonstrate how interferers with specified frequency characteristics can be synthesized at low cost for interference testing of RF communications systems. The frameworks presented in this thesis have a significant impact in enabling low-cost test and tuning of difficult-to-measure device specifications for power converter and high-speed devices.Ph.D

Imaging Microphysiometry of 2D and 3D Tissue Models: Method Development and Application

This thesis was focused on monitoring two essential parameters of life in cell and tissue culture: oxygen and pH. Oxygen tension and pH are two fundamental indicators for metabolic activity and they allow discriminating between normal and cancerous tissue. The parameters were analyzed on the one hand by using analyte-sensitive, planar sensor foils detecting changes in the microenvironment of cells and on the other hand by applying different extracellular pH values to see how cells reacted in different developmental stages or phenotypes. Four different cell lines were analyzed: (i) NRK cells representing normal cells, (ii) A549 cells which are human lung cancer cells and (iii) SK-MEL-28 and SpiCa cells which are two human skin cancer subtypes. Initial methodological investigations demonstrated the high spatial resolution of the oxygen-sensitive sensor foils. The experiments yielded highly cell line-dependent respiratory activities and oxygen consumption rates. The experiments confirmed a highly expected cell line-specific oxygen uptake and consumption reflecting that different tissue types in the body are also exposed to different oxygen tensions. Experiments carried out with pre-cultured spheroids showed differences in the emerging oxygen gradients beneath the tissue depending on: (i) previous adhesion and cultivation times, (ii) structural properties of the spheroid meaning whether it was densely packed of exhibited a softer, formable structure and (iii) the individual cell line. Vertical oxygen gradients were detected by using triangular glass prisms, with one leg of the prism being covered with the oxygen-sensitive sensor foil. The prisms were suspended in the supernatant medium above adherent cell monolayers. The device allowed for the mapping of vertical oxygen gradients which revealed emerging oxygen concentration gradients depending on the number of metabolically active cells on the surface, the height of the culture medium and the geometry of the respective cell culture vessel. Besides the detection of oxygen concentrations beneath cells as an indicator of their respiration, the pH as the second key parameter was systematically varied in the supernatant medium and several cellular phenotypes were analyzed as a function of pH. Overall, a stronger inhibition of phenotypic behavior was observed for all the cell lines under extracellular acidification than alkaline milieus could increase the phenotypic activity. On the contrary, alkaline conditions even led to a slightly lower cellular response in the case of the cancerous cells.To complete the picture, the intracellular pHi was detected as a function of well-defined extracellular pHe conditions. Intracellular pHi, analyzed with the help of the dye BCECF. The more alkaline the extracellular environment was, the more aligned were the pHi and the pHe value. The studies of this thesis highlight how important a detailed cell characterization is to understand cellular responses to certain stimulations in order to be able to revert to this knowledge in the development of targeted drug design for therapeutics and diagnostics. The last two chapters describe how the experimental techniques to monitor oxygen consumption and phenotypic behavior have been applied in toxicity studies. The influence of BPA on the respiration activity of NRK cells yielded EC50 values between (149 ± 64) µM ((76 ± 5) µM for the time intervall between 6.5 – 9 h of BPA exposure) and (159 ± 235) µM for the sensor spot (SDR®) and sensor foil (VisiSens TD) based experiments, respectively. The influence of glyphosate on the cellular respiration of NRK cells was monitored using the oxygen-sensitive sensor foil. The experiments showed a concentration-independent, slightly inhibited respiration under the exposure to pure glyphosate and a strictly concentration-dependent signal under the influence of glyphosate in the Roundup® formulation with a significantly slower respiration at high concentrations. Complementarily performed studies monitoring the acute toxicity on NRK cells yielded EC50 values between (13.8 ± 0.6) mM (glyphosate) and (4.0 ± 0.7) mM (Roundup®) detected via ECISTM and EC50 values between (19 ± 8) mM (glyphosate) and (3.0 ± 0.2) mM (Roundup®) performed via a PrestoBlueTM cell viability assay