Design of a Quasi-Adiabatic Current-Mode Neurostimulator Integrated Circuit for Deep Brain Stimulation

Electrical stimulation of neural tissues is a valuable tool in the retinal prosthesis, cardiac pacemakers, and Deep Brain Stimulation (DBS). DBS is being to treat a growing number of neurological disorders, such as movement disorder, epilepsy, and Parkinson’s disease. The role of the electronic stimulator is paramount in such application, and significant design challenges are to be met to enhance safety and reliability. A current-source based stimulator can accurately deliver a charge-balanced stimulus maintaining patient safety. In this thesis, a general-purpose current-mode neurostimulator (CMS) based upon a new quasi-adiabatic driving technique is proposed which can theoretically achieve more than 80% efficiency with the help of a dynamic high voltage supply (DHVS) as opposed to most conventional general-purpose CMS having less than 25% efficiency. The high-voltage supply is required to withstand the voltage seen across the electrodes (>10V) due to the time-varying impedance presented by the electrode-tissue interface. The overall efficiency of the designed CMS is limited by the efficiency of the DHVS. A HVDD of 15V is created by the DHVS from an input voltage (VDD) of 3V. The DHVS circuit is made by cascading five charge pump circuits using the AMI 0.5µm CMOS process. It can maintain more than 60% efficiency for a wide range of load current from 25µA to 1.4mA, with peak efficiency at 67% and this is comparable with existing specific-purpose state-of-the-art high-voltage supplies used in a current stimulator. The stimulator designed in this thesis employs a new efficient charge recycling mechanism to enhance the overall efficiency, compared to the existing state-of-the-art CMSs. Thus, the overall CMS efficiency is improved by 20% to 25%. A current source, programmable by 8-bit digital input, is also designed which has an output impedance greater than 2MΩ with a dropout voltage of only 120mV. Measurements show voltage compliance exceeding +/-15V when driving a biphasic current stimulus of 10µA to 2.5mA through a simplified R-C model of the electrode-tissue interface. The voltage compliance is defined as the maximum voltage a stimulator can apply across the electrodes to achieve neural stimulation

Integrated circuit design for implantable neural interfaces

Progress in microfabrication technology has opened the way for new possibilities in neuroscience and medicine. Chronic, biocompatible brain implants with recording and stimulation capabilities provided by embedded electronics have been successfully demonstrated. However, more ambitious applications call for improvements in every aspect of existing implementations. This thesis proposes two prototypes that advance the field in significant ways. The first prototype is a neural recording front-end with spectral selectivity capabilities that implements a design strategy that leads to the lowest reported power consumption as compared to the state of the art. The second one is a bidirectional front-end for closed-loop neuromodulation that accounts for self-interference and impedance mismatch thus enabling simultaneous recording and stimulation. The design process and experimental verification of both prototypes is presented herein

Ultra-low power mixed-signal frontend for wearable EEGs

Electronics circuits are ubiquitous in daily life, aided by advancements in the chip design industry, leading to miniaturised solutions for typical day to day problems. One of the critical healthcare areas helped by this advancement in technology is electroencephalography (EEG). EEG is a non-invasive method of tracking a person's brain waves, and a crucial tool in several healthcare contexts, including epilepsy and sleep disorders. Current ambulatory EEG systems still suffer from limitations that affect their usability. Furthermore, many patients admitted to emergency departments (ED) for a neurological disorder like altered mental status or seizures, would remain undiagnosed hours to days after admission, which leads to an elevated rate of death compared to other conditions. Conducting a thorough EEG monitoring in early-stage could prevent further damage to the brain and avoid high mortality. But lack of portability and ease of access results in a long wait time for the prescribed patients. All real signals are analogue in nature, including brainwaves sensed by EEG systems. For converting the EEG signal into digital for further processing, a truly wearable EEG has to have an analogue mixed-signal front-end (AFE). This research aims to define the specifications for building a custom AFE for the EEG recording and use that to review the suitability of the architectures available in the literature. Another critical task is to provide new architectures that can meet the developed specifications for EEG monitoring and can be used in epilepsy diagnosis, sleep monitoring, drowsiness detection and depression study. The thesis starts with a preview on EEG technology and available methods of brainwaves recording. It further expands to design requirements for the AFE, with a discussion about critical issues that need resolving. Three new continuous-time capacitive feedback chopped amplifier designs are proposed. A novel calibration loop for setting the accurate value for a pseudo-resistor, which is a crucial block in the proposed topology, is also discussed. This pseudoresistor calibration loop achieved the resistor variation of under 8.25%. The thesis also presents a new design of a curvature corrected bandgap, as well as a novel DDA based fourth-order Sallen-Key filter. A modified sensor frontend architecture is then proposed, along with a detailed analysis of its implementation. Measurement results of the AFE are finally presented. The AFE consumed a total power of 3.2A (including ADC, amplifier, filter, and current generation circuitry) with the overall integrated input-referred noise of 0.87V-rms in the frequency band of 0.5-50Hz. Measurement results confirmed that only the proposed AFE achieved all defined specifications for the wearable EEG system with the smallest power consumption than state-of-art architectures that meet few but not all specifications. The AFE also achieved a CMRR of 131.62dB, which is higher than any studied architectures.Open Acces

Applications in Electronics Pervading Industry, Environment and Society

This book features the manuscripts accepted for the Special Issue “Applications in Electronics Pervading Industry, Environment and Society—Sensing Systems and Pervasive Intelligence” of the MDPI journal Sensors. Most of the papers come from a selection of the best papers of the 2019 edition of the “Applications in Electronics Pervading Industry, Environment and Society” (APPLEPIES) Conference, which was held in November 2019. All these papers have been significantly enhanced with novel experimental results. The papers give an overview of the trends in research and development activities concerning the pervasive application of electronics in industry, the environment, and society. The focus of these papers is on cyber physical systems (CPS), with research proposals for new sensor acquisition and ADC (analog to digital converter) methods, high-speed communication systems, cybersecurity, big data management, and data processing including emerging machine learning techniques. Physical implementation aspects are discussed as well as the trade-off found between functional performance and hardware/system costs

High-Voltage Compliant, Electrode-Invariant Neural Stimulation Electronics Compatible with Low-Voltage, Bulk-CMOS Integration

Thesis (Master's)--University of Washington, 2015This work explores the challenges of implementing practical, electrical neural stimulation interfaces using modern silicon CMOS technologies. To overcome said challenges, which stem from the discrepancy between the low-voltage limitations of modern CMOS devices and the large stimulation voltages often observed at response-evoking stimulus levels, a new stimulator front-end is proposed. The high-voltage compliant front-end can reliably drive biphasic, constant-current stimulus through a wide range of electrode impedances while being safely implemented in a low-voltage, bulk-CMOS technology. The topology of the front-end is based on a sink-regulated H-bridge. Stimulus current is supplied using specialized, fully-integrated dynamic voltage supplies (DVSs), which are controlled in closed-loop to have an output voltage approximately equal to the voltage of the electrode each supplies stimulus to. The entire stimulus waveform is regulated by a single, low-voltage current-DAC, which can safely interface with the electrodes (which may be at high voltages) via specialized high-voltage adapter (HVA) circuits. To account for “capacitive-looking” electrodes and to provide unique, “electrode-invariant” performance, the front-end uses the balancing stimulus current to discharge the electrode-tissue-interface impedance (ZE), and only after full ZE discharge has been detected is a DVS used to supply the remaining balancing stimulus. In this thesis the described front-end topology and the enabling high-voltage operating circuits are presented and discussed in detail. Additionally, a stand-alone DVS circuit has been fabricated in 65nm bulk-CMOS, demonstrating the power-supplying and transient performance required by the proposed stimulator design. Another chip, featuring the entire integrated neural stimulator front-end, has also been designed in 65nm bulk-CMOS, with post-layout simulations showing ±11V compliance (approximately) across a 50μA to 2mA stimulus amplitude range. The efficacy of the proposed integrated electronics in potential neural stimulation applications is also explored using a board-level prototype and in-vivo evaluation