CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit

This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits and drawbacks, the paper proposes a synthesis approach for PWL dynamic systems, based on state-variable methods, and identifies the associated analog operators. The GmC approach, combining quasi-linear VCCS's, PWL VCCS's, and capacitors is then explored regarding the implementation of these operators. CMOS basic building blocks for the realization of the quasi-linear VCCS's and PWL VCCS's are presented and applied to design a Chua's circuit IC. The influence of GmC parasitics on the performance of dynamic PWL systems is illustrated through this example. Measured chaotic attractors from a Chua's circuit prototype are given. The prototype has been fabricated in a 2.4- mu m double-poly n-well CMOS technology, and occupies 0.35 mm/sup 2/, with a power consumption of 1.6 mW for a +or-2.5-V symmetric supply. Measurements show bifurcation toward a double-scroll Chua's attractor by changing a bias current

The Atmosphere Explorer power subsystem

The design and operation of the power subsystem for the Atmospheric Explorer spacecraft are discussed. The additional functional redundancy which was added in several component areas to improve the overall subsystem reliability is analyzed. The battery charging technique has been modified to include third electrode overcharge control. The automatic removal of all battery charge is provided to correct abnormally high battery voltages. An undervoltage detector has been added which removes all nonessential spacecraft loads when the battery voltage falls below a given level. All automatic functions can be over-ridden by ground command

Nd:YAG development for spaceborne laser ranging system

The results of the development of a unique modelocked laser device to be utilized in future NASA space-based, ultraprecision laser ranger systems are summarized. The engineering breadboard constructed proved the feasibility of the pump-pulsed, actively modelocked, PTM Q-switched Nd:YAG laser concept for the generation of subnanosecond pulses suitable for ultra-precision ranging. The laser breadboard also included a double-pass Nd:YAG amplifier and provision for a Type II KD*P frequency doubler. The specific technical accomplishment was the generation of single 150 psec, 20-mJ pulses at 10 pps at a wavelength of 1.064 micrometers with 25 dB suppression of pre-and post-pulses

Programmable CMOS Analog-to-Digital Converter Design and Testability

In this work, a programmable second order oversampling CMOS delta-sigma analog-to-digital converter (ADC) design in 0.5µm n-well CMOS processes is presented for integration in sensor nodes for wireless sensor networks. The digital cascaded integrator comb (CIC) decimation filter is designed to operate at three different oversampling ratios of 16, 32 and 64 to give three different resolutions of 9, 12 and 14 bits, respectively which impact the power consumption of the sensor nodes. Since the major part of power consumed in the CIC decimator is by the integrators, an alternate design is introduced by inserting coder circuits and reusing the same integrators for different resolutions and oversampling ratios to reduce power consumption. The measured peak signal-to-noise ratio (SNR) for the designed second order delta-sigma modulator is 75.6dB at an oversampling ratio of 64, 62.3dB at an oversampling ratio of 32 and 45.3dB at an oversampling ratio of 16. The implementation of a built-in current sensor (BICS) which takes into account the increased background current of defect-free circuits and the effects of process variation on ΔIDDQ testing of CMOS data converters is also presented. The BICS uses frequency as the output for fault detection in CUT. A fault is detected when the output frequency deviates more than ±10% from the reference frequency. The output frequencies of the BICS for various model parameters are simulated to check for the effect of process variation on the frequency deviation. A design for on-chip testability of CMOS ADC by linear ramp histogram technique using synchronous counter as register in code detection unit (CDU) is also presented. A brief overview of the histogram technique, the formulae used to calculate the ADC parameters, the design implemented in 0.5µm n-well CMOS process, the results and effectiveness of the design are described. Registers in this design are replaced by 6T-SRAM cells and a hardware optimized on-chip testability of CMOS ADC by linear ramp histogram technique using 6T-SRAM as register in CDU is presented. The on-chip linear ramp histogram technique can be seamlessly combined with ΔIDDQ technique for improved testability, increased fault coverage and reliable operation

A novel readout method for focal plane array imaging in the presence of large dark current

This research was an investigation of a novel readout method for focal plane array (FPA) optical imaging, especially for very sensitive detectors with large dark current. The readout method is based on periodically blocking the optical input enabling the removal of the dark current integration from the output. The research demonstrated that it is feasible to modulate the optical input with the designed readout circuit and thus achieve longer signal integration time to enhance the signal-to-noise ratio. Study of a proposed circuit model showed that in theory the correlated readout method could increase the output voltage swing and reduce the noise level by attenuating low frequency noise, thereby effectively improving the FPA dynamic range. Circuits based on standard CMOS circuitry were designed, simulated by PSpice, fabricated using Orbit 2µm n-well technology, and tested with a PI-4000 system. In the circuit evaluation, the output noise due to the clock switching phenomena, the gate signal feedthrough and the charge relaxation, was considered to be the critical problem. The most promising design for minimizing this problem had a CMOS current steering circuit at the input of a high CMRR operational amplifier. Simulation and test results showed that a modified capacitive transimpedance amplifier (CTIA) could subtract dark current output and reduce the output signal due to any difference between the frequencies of the optical input modulation signal and the switch modulation signal. In conclusion, the correlated readout circuit was shown to be a promising approach for advancing FPA technology

Low-cost programmable battery dischargers and application in battery model identification

This paper describes a study where a low-cost programmable battery discharger was built from basic electronic components, the popular MATLAB programming environment, and an low-cost Arduino microcontroller board. After its components and their function are explained in detail, a case study is performed to evaluate the discharger's performance. The setup is principally suitable for any type of battery cell or small packs. Here a 7.2 V NiMH battery pack including six cells is used. Consecutive discharge current pulses are applied and the terminal voltage is measured as the output. With the measured data, battery model identification is performed using a simple equivalent circuit model containing the open circuit voltage and the internal resistance. The identification results are then tested by repeating similar tests. Consistent results demonstrate accuracy of the identified battery parameters, which also confirms the quality of the measurement. Furthermore, it is demonstrated that the identification method is fast enough to be used in real-time applications

Study of Radiation-Tolerant SRAM Design

Static Random Access Memories (SRAMs) are important storage components and widely used in digital systems. Meanwhile, with the continuous development and progress of aerospace technologies, SRAMs are increasingly used in electronic systems for spacecraft and satellites. Energetic particles in space environments can cause single event upsets normally referred as soft errors in the memories, which can lead to the failure of systems. Nowadays electronics at the ground level also experience this kind of upset mainly due to cosmic neutrons and alpha particles from packaging materials, and the failure rate can be 10 to 100 times higher than the errors from hardware failures. Therefore, it is important to study the single event effects in SRAMs and develop cost-effective techniques to mitigate these errors. The objectives of this thesis are to evaluate the current mitigation techniques of single event effects in SRAMs and develop a radiation-tolerant SRAM based on the developed techniques. Various radiation sources and the mechanism of their respective effects in Complementary Metal-Oxide Semiconductors(CMOS) devices are reviewed first in the thesis. The radiation effects in the SRAMs, specifically single event effects are studied, and various mitigation techniques are evaluated. Error-correcting codes (ECC) are studied in the thesis since they can detect and correct single bit errors in the cell array, and it is a effective method with low overhead in terms of area, speed, and power. Hamming codes are selected and implemented in the design of the SRAM, to protect the cells from single event upsets in the SRAM. The simulation results show they can prevent the single bit errors in the cell arrays with low area and speed overhead. Another important and vulnerable part of SRAMs in radiation environments is the sense amplifier. It may not generate the correct output during the reading operation if it is hit by an energetic particle. A novel fault-tolerant sense amplifier is introduced and validated with simulations. The results showed that the performance of the new design can be more than ten times better than that of the reference design. When combining the SRAM cell arrays protected with ECC and the radiation-tolerant hardened sense amplifiers, the SRAM can achieve high reliability with low speed and area overhead

Power supply current [IPS] based testing of CMOS amplifier circuit with and without floating gate input transistors

This work presents a case study, which attempts to improve the fault diagnosis and testability of the power supply current based testing methodology applied to a typical two-stage CMOS operational amplifier and is extended to operational amplifier with floating gate input transistors*. The proposed test method takes the advantage of good fault coverage through the use of a simple power supply current measurement based test technique, which only needs an ac input stimulus at the input and no additional circuitry. The faults simulating possible manufacturing defects have been introduced using the fault injection transistors. In the present work, variations of ac ripple in the power supply current IPS, passing through VDD under the application of an ac input stimulus is measured to detect injected faults in the CMOS amplifier. The effect of parametric variation is taken into consideration by setting tolerance limit of ± 5% on the fault-free IPS value. The fault is identified if the power supply current, IPS falls outside the deviation given by the tolerance limit. This method presented can also be generalized to the test structures of other floating-gate MOS analog and mixed signal integrated circuits