Power conversion techniques in nanometer CMOS for low-power applications

As System-on-Chip (SoCs) in nanometer CMOS technologies grow larger, the power management process within these SoCs becomes very challenging. In the heart of this process lies the challenge of implementing energy-efficient and cost-effective DC-DC power converters. To address this challenge, this thesis studies in details three different aspects of DC-DC power converters and proposes potential solutions. First, to maximize power conversion efficiency, loss mechanisms must be studied and quantified. For that purpose, we provide comprehensive analysis and modeling of the various switching and conduction losses in low-power synchronous DC-DC buck converters in both Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM) operation, including the case with non-rail gate control of the power switches. Second, a DC-DC buck converter design with only on-chip passives is proposed and implemented in 65-nm CMOS technology. The converter switches at 588 MHz and uses a 20-nH and 300-pF on-chip inductor and capacitor respectively, and provides up to 30-mA of load at an output voltage in the range of 0.8-1.2 V. The proposed design features over 10% improvement in power conversion efficiency over a corresponding linear regulator while preserving low-cost implementation. Finally, a 40-mA buck converter design operating in the inherently-stable DCM mode for the entire load range is presented. It employs a Pulse Frequency Modulation (PFM) scheme using a Hysteretic-Assisted Adaptive Minimum On-Time (HA-AMOT) controller to automatically adapt to a wide range of operating scenarios while minimizing inductor peak current. As a result, compact silicon area, low quiescent current, high efficiency, and robust performance across all conditions can be achieved without any calibration

Small Form Factor Hybrid CMOS/GaN Buck Converters for 10W Point of Load Applications

abstract: Point of Load (PoL) converters are important components to the power distribution system in computer power supplies as well as automotive, space, nuclear, and medical electronics. These converters often require high output current capability, low form factor, and high conversion ratios (step-down) without sacrificing converter efficiency. This work presents hybrid silicon/gallium nitride (CMOS/GaN) power converter architectures as a solution for high-current, small form-factor PoL converters. The presented topologies use discrete GaN power devices and CMOS integrated drivers and controller loop. The presented power converters operate in the tens of MHz range to reduce the form factor by reducing the size of the off-chip passive inductor and capacitor. Higher conversion ratio is achieved through a fast control loop and the use of GaN power devices that exhibit low parasitic gate capacitance and minimize pulse swallowing. This work compares three discrete buck power converter architectures: single-stage, multi-phase with 2 phases, and stacked-interleaved, using components-off-the-shelf (COTS). Each of the implemented power converters achieves over 80% peak efficiency with switching speeds up-to 10MHz for high conversion ratio from 24V input to 5V output and maximum load current of 10A. The performance of the three architectures is compared in open loop and closed loop configurations with respect to efficiency, output voltage ripple, and power stage form factor. Additionally, this work presents an integrated CMOS gate driver solution in CMOS 0.35um technology. The CMOS integrated circuit (IC) includes the gate driver and the closed loop controller for directly driving a single-stage GaN architecture. The designed IC efficiently drives the GaN devices up to 20MHz switching speeds. The presented controller technique uses voltage mode control with an innovative cascode driver architecture to allow a 3.3V CMOS devices to effectively drive GaN devices that require 5V gate signal swing. Furthermore, the designed power converter is expected to operate under 400MRad of total dose, thus enabling its use in high-radiation environments for the large hadron collider at CERN and nuclear facilities.Dissertation/ThesisMasters Thesis Electrical Engineering 201

Co-design of Security Aware Power System Distribution Architecture as Cyber Physical System

The modern smart grid would involve deep integration between measurement nodes, communication systems, artificial intelligence, power electronics and distributed resources. On one hand, this type of integration can dramatically improve the grid performance and efficiency, but on the other, it can also introduce new types of vulnerabilities to the grid. To obtain the best performance, while minimizing the risk of vulnerabilities, the physical power system must be designed as a security aware system. In this dissertation, an interoperability and communication framework for microgrid control and Cyber Physical system enhancements is designed and implemented taking into account cyber and physical security aspects. The proposed data-centric interoperability layer provides a common data bus and a resilient control network for seamless integration of distributed energy resources. In addition, a synchronized measurement network and advanced metering infrastructure were developed to provide real-time monitoring for active distribution networks. A hybrid hardware/software testbed environment was developed to represent the smart grid as a cyber-physical system through hardware and software in the loop simulation methods. In addition it provides a flexible interface for remote integration and experimentation of attack scenarios. The work in this dissertation utilizes communication technologies to enhance the performance of the DC microgrids and distribution networks by extending the application of the GPS synchronization to the DC Networks. GPS synchronization allows the operation of distributed DC-DC converters as an interleaved converters system. Along with the GPS synchronization, carrier extraction synchronization technique was developed to improve the system’s security and reliability in the case of GPS signal spoofing or jamming. To improve the integration of the microgrid with the utility system, new synchronization and islanding detection algorithms were developed. The developed algorithms overcome the problem of SCADA and PMU based islanding detection methods such as communication failure and frequency stability. In addition, a real-time energy management system with online optimization was developed to manage the energy resources within the microgrid. The security and privacy were also addressed in both the cyber and physical levels. For the physical design, two techniques were developed to address the physical privacy issues by changing the current and electromagnetic signature. For the cyber level, a security mechanism for IEC 61850 GOOSE messages was developed to address the security shortcomings in the standard

Design and Control of Power Converters 2019

In this book, 20 papers focused on different fields of power electronics are gathered. Approximately half of the papers are focused on different control issues and techniques, ranging from the computer-aided design of digital compensators to more specific approaches such as fuzzy or sliding control techniques. The rest of the papers are focused on the design of novel topologies. The fields in which these controls and topologies are applied are varied: MMCs, photovoltaic systems, supercapacitors and traction systems, LEDs, wireless power transfer, etc

Efficient power management circuits for energy harvesting applications

Low power IoT devices are growing in numbers and by 2020 there will be more than 25 Billion of those in areas such as wearables, smart homes, remote surveillance, transportation and industrial systems, including many others. Many IoT electronics either will operate from stand-alone energy supply (e.g., battery) or be self-powered by harvesting from ambient energy sources or have both options. Harvesting sustainable energy from ambient environment plays significant role in extending the operation lifetime of these devices and hence, lower the maintenance cost of the system, which in turn help make them integral to simpler systems. Both for battery-powered and harvesting capable systems, efficient power delivery unit remains an essential component for maximizing energy efficiency. The goal of this research is to investigate the challenges of energy delivery for low power electronics considering both energy harvesting as well as battery-powered conditions and to address those challenges. Different challenges of energy harvesting from low voltage energy sources based on the limitations of the sources, the type of the regulator used and the pattern of the load demands have been investigated. Different aspects of the each challenges are further investigated to seek optimized solutions for both load specific and generalized applications. A voltage boost mechanism is chosen as the primary mechanism to investigate and to addressing those challenges, befitting the need for low power applications which often rely on battery voltage or on low voltage energy harvesting sources. Additionally, a multiple output buck regulator is also discussed. The challenges analyzed include very low voltage start up issues for an inductive boost regulator, cascading of boost regulator stages, and reduction of the number of external component through reusing those. Design techniques for very high conversion ratio, bias current reduction with autonomous bias gating, battery-less cold start, component and power stage multiplexing for reconfigurable and multi-domain regulators are presented. Measurement results from several silicon prototypes are also presented.Ph.D

Design Space Evaluation for Resonant and Hard-charged Switched Capacitor Converters

USB Power Delivery enables a fixed ratio converter to operate over a wider range of output voltages by varying the input voltage. Of the DC/DC step-down converters powered from this type of USB, the hard-charged Switched Capacitor circuit is of interest to industry for its potential high power density. However implementation can be limited by circuit efficiency. In fully resonant mode, the efficiency can be improved while also enabling current regulation. This expands the possible applications into battery chargers and eliminates the need for a two-stage converter.In this work, the trade-off in power loss and area between the hard-charged and fully resonant switched capacitor circuit is explored using a technique that remains agnostic to inductor technology. The loss model for each converter is presented as well as discussion on the restrained design space due to parasitics in the passive components. The results are validated experimentally using GaN-based prototype converters and the respective design spaces are analyzed