5,711 research outputs found
Tactile sensing chips with POSFET array and integrated interface electronics
This work presents the advanced version of novel POSFET (Piezoelectric Oxide Semiconductor Field Effect Transistor) devices based tactile sensing chip. The new version of the tactile sensing chip presented here comprises of a 4 x 4 array of POSFET touch sensing devices and integrated interface electronics (i.e. multiplexers, high compliance current sinks and voltage output buffers). The chip also includes four temperature diodes for the measurement of contact temperature. Various components on the chip have been characterized systematically and the overall operation of the tactile sensing system has been evaluated. With new design the POSFET devices have improved performance (i.e. linear response in the dynamic contact forces range of 0.01–3N and sensitivity (without amplification) of 102.4 mV/N), which is more than twice the performance of their previous implementations. The integrated interface electronics result in reduced interconnections which otherwise would be needed to connect the POSFET array with off-chip interface electronic circuitry. This research paves the way for CMOS (Complementary Metal Oxide Semiconductor) implementation of full on-chip tactile sensing systems based on POSFETs
An Energy-Efficient, Dynamic Voltage Scaling Neural Stimulator for a Proprioceptive Prosthesis
Accepted versio
A Modular Programmable CMOS Analog Fuzzy Controller Chip
We present a highly modular fuzzy inference analog CMOS chip architecture with on-chip digital programmability. This chip consists of the interconnection of parameterized instances of two different kind of blocks, namely label blocks and rule blocks. The architecture realizes a lattice partition of the universe of discourse, which at the hardware level means that the fuzzy labels associated to every input (realized by the label blocks) are shared among the rule blocks. This reduces the area and power consumption and is the key point for chip modularity. The proposed architecture is demonstrated through a 16-rule two input CMOS 1-μm prototype which features an operation speed of 2.5 Mflips (2.5×10^6 fuzzy inferences per second) with 8.6 mW power consumption. Core area occupation of this prototype is of only 1.6 mm 2 including the digital control and memory circuitry used for programmability. Because of the architecture modularity the number of inputs and rules can be increased with any hardly design effort.This work was
supported in part by the Spanish C.I.C.Y.T under Contract TIC96-1392-C02-
02 (SIVA)
High-performance condenser microphone with fully integrated CMOS amplifier and DC-DC voltage converter
The development of a capacitive microphone with an integrated detection circuit is described. The condenser microphone is made by micromachining of polyimide on silicon. Therefore, the structure can be realized by postprocessing on substrates containing integrated circuits (IC's), independently of the IC process, integrated microphones with excellent performances have been realized on a CMOS substrate containing dc-dc voltage converters and preamplifiers. The measured sensitivity of the integrated condenser microphone was 10 mV/Pa, and the equivalent noise level (ENL) was 27 dB(A) re. 20 ¿Pa for a power supply voltage of 1.9 V, which was measured with no bias voltage applied to the microphone. Furthermore, a back chamber of infinite volume was used in all reported measurements and simulation
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SiOx-based resistive switching memory integrated in nanopillar structure fabricated by nanosphere lithography
textA highly compact, one diode-one resistor (1D-1R) SiOx-based resistive switching memory device with nano-pillar architecture has been achieved for the first time using nano-sphere lithography. The average nano-pillar height and diameter are 1.3 μm and 130 nm, respectively. Low-voltage electroforming using DC bias and AC pulse response in the 50ns regime demonstrate good potential for high-speed, low-energy nonvolatile memory. Nano-sphere deposition, oxygen-plasma isolation, and nano-pillar formation by deep-Si-etching are studied and optimized for the 1D-1R configurations. Excellent electrical performance, data retention and the potential for wafer-scale integration are promising for future non-volatile memory applications.Materials Science and Engineerin
An Extended CMOS ISFET Model Incorporating the Physical Design Geometry and the Effects on Performance and Offset Variation
This paper presents an extended model for the CMOS-based ion-sensitive field-effect transistor, incorporating design parameters associated with the physical geometry of the device. This can, for the first time, provide a good match between calculated and measured characteristics by taking into account the effects of nonidealities such as threshold voltage variation and sensor noise. The model is evaluated through a number of devices with varying design parameters (chemical sensing area and MOSFET dimensions) fabricated in a commercially available 0.35-µm CMOS technology. Threshold voltage, subthreshold slope, chemical sensitivity, drift, and noise were measured and compared with the simulated results. The first- and second-order effects are analyzed in detail, and it is shown that the sensors' performance was in agreement with the proposed model
Characterisation of AMS H35 HV-CMOS monolithic active pixel sensor prototypes for HEP applications
Monolithic active pixel sensors produced in High Voltage CMOS (HV-CMOS)
technology are being considered for High Energy Physics applications due to the
ease of production and the reduced costs. Such technology is especially
appealing when large areas to be covered and material budget are concerned.
This is the case of the outermost pixel layers of the future ATLAS tracking
detector for the HL-LHC. For experiments at hadron colliders, radiation
hardness is a key requirement which is not fulfilled by standard CMOS sensor
designs that collect charge by diffusion. This issue has been addressed by
depleted active pixel sensors in which electronics are embedded into a large
deep implantation ensuring uniform charge collection by drift. Very first small
prototypes of hybrid depleted active pixel sensors have already shown a
radiation hardness compatible with the ATLAS requirements. Nevertheless, to
compete with the present hybrid solutions a further reduction in costs
achievable by a fully monolithic design is desirable. The H35DEMO is a large
electrode full reticle demonstrator chip produced in AMS 350 nm HV-CMOS
technology by the collaboration of Karlsruher Institut f\"ur Technologie (KIT),
Institut de F\'isica d'Altes Energies (IFAE), University of Liverpool and
University of Geneva. It includes two large monolithic pixel matrices which can
be operated standalone. One of these two matrices has been characterised at
beam test before and after irradiation with protons and neutrons. Results
demonstrated the feasibility of producing radiation hard large area fully
monolithic pixel sensors in HV-CMOS technology. H35DEMO chips with a substrate
resistivity of 200 cm irradiated with neutrons showed a radiation
hardness up to a fluence of ncm with a hit efficiency of
about 99% and a noise occupancy lower than hits in a LHC bunch
crossing of 25ns at 150V
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