Topological Interference Management through Index Coding

This work studies linear interference networks, both wired and wireless, with no channel state information at the transmitters (CSIT) except a coarse knowledge of the end-to-end one-hop topology of the network that only allows a distinction between weak (zero) and significant (non-zero) channels and no further knowledge of the channel coefficients' realizations. The network capacity (wired) and DoF (wireless) are found to be bounded above by the capacity of an index coding problem for which the antidote graph is the complement of the given interference graph. The problems are shown to be equivalent under linear solutions. An interference alignment perspective is then used to translate the existing index coding solutions into the wired network capacity and wireless network DoF solutions, as well as to find new and unified solutions to different classes of all three problems.Comment: Revised for the IEEE Transactions on Information Theor

Cyclic Interference Alignment and Cancellation in 3-User X-Networks with Minimal Backhaul

We consider the problem of Cyclic Interference Alignment (IA) on the 3-user X-network and show that it is infeasible to exactly achieve the upper bound of $\frac{K^2}{2K-1}=\frac{9}{5}$ degrees of freedom for the lower bound of n=5 signalling dimensions and K=3 user-pairs. This infeasibility goes beyond the problem of common eigenvectors in invariant subspaces within spatial IA. In order to gain non-asymptotic feasibility with minimal intervention, we first investigate an alignment strategy that enables IA by feedforwarding a subset of messages with minimal rate. In a second step, we replace the proposed feedforward strategy by an analogous Cyclic Interference Alignment and Cancellation scheme with a backhaul network on the receiver side and also by a dual Cyclic Interference Neutralization scheme with a backhaul network on the transmitter side.Comment: 8 pages, short version submitted to ISIT 201

Achievable rates for relay networks using superposition coding

We investigate the superposition strategy and its usefulness in terms of achievable information theoretic rates. The achievable rate of the superposition of block Markov encoding (decode-forward) and side information encoding (compress-forward) for the three-node Gaussian relay channel is analyzed. It is generally believed that superposition can out perform decode-forward or compress-forward due to its generality. We prove that within the class of Gaussian distributions, this is not the case: the superposition scheme only achieves a rate that is equal to the maximum of the rates achieved by decode-forward or compress-forward individually. We use the insight gathered on superposition forward scheme and devise a new coding scheme. The superposition coding scheme for communication over a network, combines partial decode-forward with noisy network coding. This hybrid scheme is termed as superposition noisy network coding. The novel coding scheme is designed and analyzed for a single relay channel, single source multicast network and multiple source multicast network. The special cases of Gaussian single relay channel and two way relay channel are analyzed for superposition noisy network coding. The achievable rate of the proposed scheme is higher than the existing schemes of noisy network coding, compress-forward and binning

Design Trade-offs for reliable On-Chip Wireless Interconnects in NoC Platforms

The massive levels of integration following Moore\u27s Law making modern multi-core chips prevail in various domains ranging from scientific applications to bioinformatics applications for consumer electronics. With higher and higher number of cores on the same die traditional bus based interconnections are no longer a scalable communication infrastructure. On-chip networks were proposed enabled a scalable plug-and-play mechanism for interconnecting hundreds of cores on the same chip. Wired interconnects between the cores in a traditional Network-on-Chip (NoC) system, becomes a bottleneck with increase in the number of cores thereby increasing the latency and energy to transmit signals over them. Hence, there has been many alternative emerging interconnect technologies proposed, namely, 3D, photonic and multi-band RF interconnects. Although they provide better connectivity, higher speed and higher bandwidth compared to wired interconnects; they also face challenges with heat dissipation and manufacturing difficulties. On-chip wireless interconnects is one other alternative proposed which doesn\u27t need physical interconnection layout as data travels over the wireless medium. They are integrated into a hybrid NOC architecture consisting of both wired and wireless links, which provides higher bandwidth, lower latency, lesser area overhead and reduced energy dissipation in communication. An efficient media access control (MAC) scheme is required to enhance the utilization of the available bandwidth. A token-passing protocol proposed to grant access of the wireless channel to competing transmitters. This limits the number of simultaneous users of the communication channel to one although multiple wireless hubs are deployed over the chip. In principle, a Frequency Division Multiple Access (FDMA) based medium access scheme would improve the utilization of the wireless resources. However, this requires design of multiple very precise, high frequency transceivers in non-overlapping frequency channels. Therefore, the scalability of this approach is limited by the state-of-the-art in transceiver design. The Code Division Multiple Access (CDMA) enables multiple transmitter-receiver pairs to send data over the wireless channel simultaneously. The CDMA protocol can significantly increase the performance of the system while lowering the energy dissipation in data transfer. The CDMA based MAC protocol outperforms the wired counterparts and several other wireless architectures proposed in literature in terms of bandwidth and packet energy dissipation. However, the reliability of CDMA based wireless NoC\u27s is limited, as the probability of error is eminent due to synchronization delays at the receiver. The thesis proposes the use of an advanced filter which improves the performance and also reduces the error due to synchronization delays. This thesis also proposes investigation of various channel modulation schemes on token passing wireless NoC\u27s to examine the performance and reliability of the system. The trade-off between performance and energy are established for the various conditions. The results are obtained using a modified cycle accurate simulator

On Multicast in Asynchronous Networks-on-Chip: Techniques, Architectures, and FPGA Implementation

In this era of exascale computing, conventional synchronous design techniques are facing unprecedented challenges. The consumer electronics market is replete with many-core systems in the range of 16 cores to thousands of cores on chip, integrating multi-billion transistors. However, with this ever increasing complexity, the traditional design approaches are facing key issues such as increasing chip power, process variability, aging, thermal problems, and scalability. An alternative paradigm that has gained significant interest in the last decade is asynchronous design. Asynchronous designs have several potential advantages: they are naturally energy proportional, burning power only when active, do not require complex clock distribution, are robust to different forms of variability, and provide ease of composability for heterogeneous platforms. Networks-on-chip (NoCs) is an interconnect paradigm that has been introduced to deal with the ever-increasing system complexity. NoCs provide a distributed, scalable, and efficient interconnect solution for today’s many-core systems. Moreover, NoCs are a natural match with asynchronous design techniques, as they separate communication infrastructure and timing from the computational elements. To this end, globally-asynchronous locally-synchronous (GALS) systems that interconnect multiple processing cores, operating at different clock speeds, using an asynchronous NoC, have gained significant interest. While asynchronous NoCs have several advantages, they also face a key challenge of supporting new types of traffic patterns. Once such pattern is multicast communication, where a source sends packets to arbitrary number of destinations. Multicast is not only common in parallel computing, such as for cache coherency, but also for emerging areas such as neuromorphic computing. This important capability has been largely missing from asynchronous NoCs. This thesis introduces several efficient multicast solutions for these interconnects. In particular, techniques, and network architectures are introduced to support high-performance and low-power multicast. Two leading network topologies are the focus: a variant mesh-of-trees (MoT) and a 2D mesh. In addition, for a more realistic implementation and analysis, as well as significantly advancing the field of asynchronous NoCs, this thesis also targets synthesis of these NoCs on commercial FPGAs. While there has been significant advances in FPGA technologies, there has been only limited research on implementing asynchronous NoCs on FPGAs. To this end, a systematic computeraided design (CAD) methodology has been introduced to efficiently and safely map asynchronous NoCs on FPGAs. Overall, this thesis makes the following three contributions. The first contribution is a multicast solution for a variant MoT network topology. This topology consists of simple low-radix switches, and has been used in high-performance computing platforms. A novel local speculation technique is introduced, where a subset of the network’s switches are speculative that always broadcast every packet. These switches are very simple and have high performance. Speculative switches are surrounded by non-speculative ones that route packets based on their destinations and also throttle any redundant copies created by the former. This hybrid network architecture achieved significant performance and power benefits over other multicast approaches. The second contribution is a multicast solution for a 2D-mesh topology, which is more complex with higher-radix switches and also is more commonly used. A novel continuous-time replication strategy is introduced to optimize the critical multi-way forking operation of a multicast transmission. In this technique, a multicast packet is first stored in an input port of a switch, from where it is sent through distinct output ports towards different destinations concurrently, at each output’s own rate and in continuous time. This strategy is shown to have significant latency and energy benefits over an approach that performs multicast using multiple distinct serial unicasts to each destination. Finally, a systematic CAD methodology is introduced to synthesize asynchronous NoCs on commercial FPGAs. A two-fold goal is targeted: correctness and high performance. For ease of implementation, only existing FPGA synthesis tools are used. Moreover, since asynchronous NoCs involve special asynchronous components, a comprehensive guide is introduced to map these elements correctly and efficiently. Two asynchronous NoC switches are synthesized using the proposed approach on a leading Xilinx FPGA in 28 nm: one that only handles unicast, and the other that also supports multicast. Both showed significant energy benefits with some performance gains over a state-of-the-art synchronous switch

Information Networks with in-Block Memory

A class of channels is introduced for which there is memory inside blocks of a specified length and no memory across the blocks. The multi-user model is called an information network with in-block memory (NiBM). It is shown that block-fading channels, channels with state known causally at the encoder, and relay networks with delays are NiBMs. A cut-set bound is developed for NiBMs that unifies, strengthens, and generalizes existing cut bounds for discrete memoryless networks. The bound gives new finite-letter capacity expressions for several classes of networks including point-to-point channels, and certain multiaccess, broadcast, and relay channels. Cardinality bounds on the random coding alphabets are developed that improve on existing bounds for channels with action-dependent state available causally at the encoder and for relays without delay. Finally, quantize-forward network coding is shown to achieve rates within an additive gap of the new cut-set bound for linear, additive, Gaussian noise channels, symmetric power constraints, and a multicast session.Comment: Paper to appear in the IEEE Transactions on Information Theor

Heterogeneous Cloud Systems Based on Broadband Embedded Computing

Computing systems continue to evolve from homogeneous systems of commodity-based servers within a single data-center towards modern Cloud systems that consist of numerous data-center clusters virtualized at the infrastructure and application layers to provide scalable, cost-effective and elastic services to devices connected over the Internet. There is an emerging trend towards heterogeneous Cloud systems driven from growth in wired as well as wireless devices that incorporate the potential of millions, and soon billions, of embedded devices enabling new forms of computation and service delivery. Service providers such as broadband cable operators continue to contribute towards this expansion with growing Cloud system infrastructures combined with deployments of increasingly powerful embedded devices across broadband networks. Broadband networks enable access to service provider Cloud data-centers and the Internet from numerous devices. These include home computers, smart-phones, tablets, game-consoles, sensor-networks, and set-top box devices. With these trends in mind, I propose the concept of broadband embedded computing as the utilization of a broadband network of embedded devices for collective computation in conjunction with centralized Cloud infrastructures. I claim that this form of distributed computing results in a new class of heterogeneous Cloud systems, service delivery and application enablement. To support these claims, I present a collection of research contributions in adapting distributed software platforms that include MPI and MapReduce to support simultaneous application execution across centralized data-center blade servers and resource-constrained embedded devices. Leveraging these contributions, I develop two complete prototype system implementations to demonstrate an architecture for heterogeneous Cloud systems based on broadband embedded computing. Each system is validated by executing experiments with applications taken from bioinformatics and image processing as well as communication and computational benchmarks. This vision, however, is not without challenges. The questions on how to adapt standard distributed computing paradigms such as MPI and MapReduce for implementation on potentially resource-constrained embedded devices, and how to adapt cluster computing runtime environments to enable heterogeneous process execution across millions of devices remain open-ended. This dissertation presents methods to begin addressing these open-ended questions through the development and testing of both experimental broadband embedded computing systems and in-depth characterization of broadband network behavior. I present experimental results and comparative analysis that offer potential solutions for optimal scalability and performance for constructing broadband embedded computing systems. I also present a number of contributions enabling practical implementation of both heterogeneous Cloud systems and novel application services based on broadband embedded computing

QoS-based multipath routing for the Internet

The new generation of network services is being developed for incorporation in communication infrastructure. These services, generally called Quality of Services (QoS), should accommodate data file, video, and audio applications. The different performance requirements of these applications necessitate a re-examination of the main architectural components of today\u27s networks, which were designed to support traditional data applications. Routing, which determines the sequence of network nodes a packet traverses between source and destination, is one such component. Here, we examine the potential routing problems in future Internet and discuss the advantages of class-based multi-path routing methods. The result is a new approach to routing in packet-switched networks, which is called Two-level Class-based Multipath routing with Prediction (TCMP). In TCMP, we compute multiple paths between each source and destination based on link propagation delay and bottleneck bandwidth. A leaky bucket is adopted in each router to monitor the bottleneck bandwidth on equal paths during the network\u27s stable period, and to guide its traffic forwarDing The TCMP can avoid frequent flooding of routing information in a dynamic routing method; therefore, it can be applied to large network topologies