Using Building Blocks to Design Analog Neuro-Fuzzy Controllers

We present a parallel architecture for fuzzy controllers and a methodology for their realization as analog CMOS chips for low- and medium-precision applications. These chips can be made to learn through the adaptation of electrically controllable parameters guided by a dedicated hardware-compatible learning algorithm. Our designs emphasize simplicity at the circuit level—a prerequisite for increasing processor complexity and operation speed. Examples include a three-input, four-rule controller chip in 1.5-μm CMOS, single-poly, double-metal technology

CMOS design of adaptive fuzzy ASICs using mixed-signal circuits

Analog circuits are natural candidates to design fuzzy chips with optimum speed/power figures for precision up to about 1%. This paper presents a methodology and circuit blocks to realize fuzzy controllers in the form of analog CMOS chips. These chips can be made to adapt their function through electrical control. The proposed design methodology emphasizes modularity and simplicity at the circuit level - prerequisites to increasing processor complexity and operation speed. The paper include measurements from a silicon prototype of a fuzzy controller chip in CMOS 1.5 /spl mu/m single-poly technology

A Modular Programmable CMOS Analog Fuzzy Controller Chip

We present a highly modular fuzzy inference analog CMOS chip architecture with on-chip digital programmability. This chip consists of the interconnection of parameterized instances of two different kind of blocks, namely label blocks and rule blocks. The architecture realizes a lattice partition of the universe of discourse, which at the hardware level means that the fuzzy labels associated to every input (realized by the label blocks) are shared among the rule blocks. This reduces the area and power consumption and is the key point for chip modularity. The proposed architecture is demonstrated through a 16-rule two input CMOS 1-μm prototype which features an operation speed of 2.5 Mflips (2.5×10^6 fuzzy inferences per second) with 8.6 mW power consumption. Core area occupation of this prototype is of only 1.6 mm 2 including the digital control and memory circuitry used for programmability. Because of the architecture modularity the number of inputs and rules can be increased with any hardly design effort.This work was supported in part by the Spanish C.I.C.Y.T under Contract TIC96-1392-C02- 02 (SIVA)

Modular Design of Adaptive Analog CMOS Fuzzy Controller Chips

Analog circuits are natural candidates to design fuzzy chips with optimum speed/power figures for precision up to about 1%. This paper presents a methodology and circuit blocks to realize fuzzy controllers in the form of analog CMOS chips. These chips can be made to adapt their function through electrical control. The proposed design methodology emphasizes modularity and simplicity at the circuit level -- prerequisites to increasing processor complexity and operation speed. The paper include measurements from a silicon prototype of a fuzzy controller chip in CMOS 1.5μm single-poly technology

A basic building block approach to CMOS design of analog neuro/fuzzy systems

Outlines a systematic approach to design fuzzy inference systems using analog integrated circuits in standard CMOS VLSI technologies. The proposed circuit building blocks are arranged in a layered neuro/fuzzy architecture composed of 5 layers: fuzzification, T-norm, normalization, consequent, and output. Inference is performed by using Takagi and Sugeno's (1989) IF-THEN rules, particularly where the rule's output contains only a constant term-a singleton. A simple CMOS circuit with tunable bell-like transfer characteristics is used for the fuzzification. The inputs to this circuit are voltages while the outputs are currents. Circuit blocks proposed for the remaining layers operate in the current-mode domain. Innovative circuits are proposed for the T-norm and normalization layers. The other two layers use current mirrors and KCL. All the proposed circuits emphasize simplicity at the circuit level-a prerequisite to increasing system level complexity and operation speed. A 3-input, 4-rule controller has been designed for demonstration purposes in a 1.6 /spl mu/m CMOS single-poly, double-metal technology. We include measurements from prototypes of the membership function block and detailed HSPICE simulations of the whole controller. These results operation speed in the range of 5 MFLIPS (million fuzzy logic inferences per second) with systematic errors below 1%

A 16 [email protected] Mixed-Signal Programmable Fuzzy Controller CMOS-1μm Chip

We present a fuzzy inference chip capable to evaluate 16 programmable rules at a speed of 2.5Mflips (2.5 × 10 6 fuzzy inferences per second) with 8.6mW power consumption. It occupies 2.89mm 2 (including pads) in a CMOS 1μm single-poly technology. Measurements are given to demonstrate its performance. All the operations needed for fuzzy inference are realized on-chip using analog circuitry compatible with standard VLSI CMOS technologies. On-chip digital control and memory circuitry is also incorporated for programmability. The chip architecture and circuitry are based on our design methodology for neurofuzzy systems reported in [1]. A few architectural modifications are made to share circuitry among rules and, thus, obtain reduced area and power consumption. The chip parameters can be learned in situ, for operation in a changing environment, by using dedicated hardware-compatible learning algorithms [1][8

Regression between headmaster leadership, task load and job satisfaction of special education integration program teacher

Managing school is a daunting task for a headmaster. This responsibility is exacerbated when it involves the Special Education Integration Program (SEIP). This situation requires appropriate and effective leadership in addressing some of the issues that are currently taking place at SEIP such as task load and job satisfaction. This study aimed to identify the influence of headmaster leadership on task load and teacher job satisfaction at SEIP. This quantitative study was conducted by distributing 400 sets of randomized questionnaires to SEIP teachers across Malaysia through google form. The data obtained were then analyzed using Structural Equation Modeling (SEM) and AMOS software. The results show that there is a significant positive effect on the leadership of the headmaster and the task load of the teacher. Likewise, the construct of task load and teacher job satisfaction has a significant positive effect. However, for the construct of headmaster leadership and teacher job satisfaction, there was no significant positive relationship. This finding is very important as a reference to the school administration re-evaluating their leadership so as not to burden SEIP teachers and to give them job satisfaction. In addition, the findings of this study can also serve as a guide for SEIP teachers to increase awareness of the importance of managing their tasks. This study also focused on education leadership in general and more specifically on special education leadership

Learning in neuro/fuzzy analog chips

This paper focus on the design of adaptive mixed-signal fuzzy chips. These chips have parallel architecture and feature electrically-controlable surface maps. The design methodology is based on the use of composite transistors - modular and well suited for design automation. This methodology is supported by dedicated, hardware-compatible learning algorithms that combine weight-perturbation and outstar

Towards the IC implementation of adaptive fuzzy systems

The required building blocks of CMOS fuzzy chips capable of performing as adaptive fuzzy systems are described in this paper. The building blocks are designed with mixed-signal current-mode cells that contain low-resolution A/D and D/A converters based on current mirrors. These cells provide the chip with an analog-digital programming interface. They also perform as computing elements of the fuzzy inference engine that calculate the output signal in either analog or digital formats, thus easing communication of the chip with digital processing environments and analog actuators. Experimental results of a 9-rule prototype integrated in a 2.4-μm CMOS process are included. It has a digital interface to program the antecedents and consequents and a mixed-signal output interface. The proposed design approach enables the CMOS realization of low-cost and high-inference fuzzy systems able to cope with complex processes through adaptation. This is illustrated with simulated results of an application to the on-line identification of a nonlinear dynamical plant