45 research outputs found

    Characterization of 28 nm FDSOI MOS and application to the design of a low-power 2.4 GHz LNA

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    IoT is expected to connect billions of devices all over world in the next years, and in a near future, it is expected to use LR-WPAN in a wide variety of applications. Not all the devices will require of high performance but will require of low power hungry systems since most of them will be powered with a battery. Conventional CMOS technologies cannot cover these needs even scaling it to very small regimes, which appear other problems. Hence, new technologies are emerging to cover the needs of this devices. One promising technology is the UTBB FDSOI, which achieves good performance with very good energy efficiency. This project characterizes this technology to obtain a set of parameters of interest for analog/RF design. Finally, with the help of a low-power design methodology (gm/Id approach), a design of an ULP ULV LNA is performed to check the suitability of this technology for IoT

    RF techniques for IEEE 802.15.4: circuit design and device modelling

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    The RF circuitry in the physical layer of any wireless communication node is arguably its most important part. The front-end radio is the hardware that enables communication by transmitting and receiving information. Without a robust and high performance front-end, all other higher layers of signal processing and data handling in a wireless network are irrelevant. This thesis investigates the radio circuitry of wireless-networked nodes, and introduces several proposals for improvement. As an emerging market, analysis starts by examining available and ratified network standards suitable for low power applications. After identifying the IEEE 802.15.4 standard (commercially known as ZigBee) as the one of choice, and analysing several front-end architectures on which its transceiver circuitry can be based, an application, the Tyre Pressure Monitoring System (TPMS) is selected to examine the capabilities of the standard and its most suitable architecture in satisfying the application’s requirements. From this compatibility analysis, the most significant shortcomings are identified as interference and power consumption. The work presented in this thesis focuses on the power consumption issues. A comparison of available high frequency transistor technologies concludes Silicon CMOS to be the most appropriate solution for the implementation of low cost and low power ZigBee transceivers. Since the output power requirement of ZigBee is relatively modest, it is possible to consider the design of a single amplifier block which can act as both a Low Noise Amplifier (LNA) in the receiver chain and a Power Amplifier (PA) on the transmitter side. This work shows that by employing a suitable design methodology, a single dual-function amplifier can be realised which meets the required performance specification. In this way, power consumption and chip area can both be reduced, leading to cost savings so vital to the widespread utilisation of the ZigBee standard. Given the importance of device nonlinearity in such a design, a new transistor model based on independent representation of each of the transistor’s nonlinear elements is developed with the aim of quantifying the individual contribution of each of the transistors nonlinear elements, to the total distortion. The methodology to the design of the dual functionality (LNA/PA) amplifier starts by considering various low noise amplifier architectures and comparing them in terms of the trade-off between noise (required for LNA operation) and linearity (important for PA operation), and then examining the behaviour of the selected architecture (the common-source common-gate cascode) at higher than usual input powers. Due to the need to meet the far apart performance requirements of both the LNA and PA, a unique amplifier design methodology is developed The design methodology is based on simultaneous graphical visualisation of the relationship between all relevant performance parameters and corresponding design parameters. A design example is then presented to demonstrate the effectiveness of the methodology and the quality of trade-offs it allows the designer to make. The simulated performance of the final amplifier satisfies both the requirements of ZigBee’s low noise and power amplification. At 2.4GHz, the amplifier is predicted to have 1.6dB Noise Figure (NF), 6dBm Input-referred 3rd-order Intercept Point (IIP3), and 1dB compression point of -3.5dBm. In low power operation, it is predicted to have 10dB gain, consuming only 8mW. At the higher input power of 0dBm, it is predicted to achieve 24% Power-Added Efficiency (PAE) with 8dB gain and 22mW power consumption. Finally, this thesis presents a set of future research proposals based on problems identified throughout its development

    Ultra Small Antenna and Low Power Receiver for Smart Dust Wireless Sensor Networks

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    Wireless Sensor Networks have the potential for profound impact on our daily lives. Smart Dust Wireless Sensor Networks (SDWSNs) are emerging members of the Wireless Sensor Network family with strict requirements on communication node sizes (1 cubic centimeter) and power consumption (< 2mW during short on-states). In addition, the large number of communication nodes needed in SDWSN require highly integrated solutions. This dissertation develops new design techniques for low-volume antennas and low-power receivers for SDWSN applications. In addition, it devises an antenna and low noise amplifier co-design methodology to increase the level of design integration, reduce receiver noise, and reduce the development cycle. This dissertation first establishes stringent principles for designing SDWSN electrically small antennas (ESAs). Based on these principles, a new ESA, the F-Inverted Compact Antenna (FICA), is designed at 916MHz. This FICA has a significant advantage in that it uses a small-size ground plane. The volume of this FICA (including the ground plane) is only 7% of other state-of-the-art ESAs, while its efficiency (48.53%) and gain (-1.38dBi) are comparable to antennas of much larger dimensions. A physics-based circuit model is developed for this FICA to assist system level design at the earliest stage, including optimization of the antenna performance. An antenna and low noise amplifier (LNA) co-design method is proposed and proven to be valid to design low power LNAs with the very low noise figure of only 1.5dB. To reduce receiver power consumption, this dissertation proposes a novel LNA active device and an input/ouput passive matching network optimization method. With this method, a power efficient high voltage gain cascode LNA was designed in a 0.13um CMOS process with only low quality factor inductors. This LNA has a 3.6dB noise figure, voltage gain of 24dB, input third intercept point (IIP3) of 3dBm, and power consumption of 1.5mW at 1.0V supply voltage. Its figure of merit, using the typical definition, is twice that of the best in the literature. A full low power receiver is developed with a sensitivity of -58dBm, chip area of 1.1mm2, and power consumption of 2.85mW

    Design of Low-Power Short-Distance Transceiver for Wireless Sensor Networks

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    Ph.DDOCTOR OF PHILOSOPH

    Stratégie d'alimentation pour les SoCs RF très faible consommation

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    Les réseaux de capteurs sans fil nécessitent des fonctions de calcul et de transmissionradio associées à chaque capteur. Les SoCs RF intégrant ces fonctions doivent avoir uneautonomie la plus grande possible et donc une très faible consommation. Aujourd'hui, leursperformances énergétiques pourraient être fortement améliorées par des systèmes d'alimentationinnovants. En effet, les circuits d'alimentation remplissent leur fonction classique de conversiond'énergie mais aussi des fonctions d'isolation des blocs RF et digitaux. Leurs performancess'évaluent donc en termes d'efficacité énergétique et de réponse transitoire mais aussi d'isolationentre blocs et de réjection de bruit.Ce travail de thèse concerne l'intégration du système de gestion et de distribution del énergie aux différents blocs RF d un émetteur/récepteur en élaborant une méthodologie topdown pour déterminer la sensibilité de chaque bloc à son alimentation et en construisant unearchitecture innovante et dynamique de gestion/distribution de l'énergie sur le SoC. Cetteméthodologie repose sur la disponibilité de régulateurs de tension présentant des performancesadaptées. Un deuxième volet du travail de thèse a donc été de réaliser un régulateur linéaire detype LDO à forte réjection sur une bande passante relativement large et bien adapté àl'alimentation de blocs RF très sensibles aux bruits de l'alimentation.Wireless sensor networks require calculation functions and radiofrequencytransmission modules within each sensor. RF SoCs integrating these functions must have thebiggest battery life and so a very small consumption. Today, innovative power managementsystems could highly enhance the energy performances of this type of RF SoC. Indeed, thesepower systems perform energy conversion and also the isolation functions of RF and digitalblocks. Their features are thus estimated in terms of energy efficiency, transient response and alsoisolation between blocks and noise rejection.This thesis work concerns the integration of the power management systems and itsdistribution channels into different ultra-low-power SoCs. This was achieved mainly thanks to thedevelopment of a new top-down approach. This new methodology consists of determining thesensibility of every block to its power supply and of designing an innovative and dynamicarchitecture of power management circuits on the SoC. This study ends up in the implementationof a very efficient low dropout (LDO) regulator for noise-sensitive low-current RF blocks inmixed SoC applications. The fabricated prototype achieves a high power supply rejection for awide range of frequencies.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

    A wireless 802.11 condition monitoring sensor for electrical substation environments

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    The work reported in this thesis is concerned with the design, development and testing of a wireless 802.11 condition monitoring sensor for an electrical substation environments. The work includes a comprehensive literature review and the design and development of a novel continuous wireless data acquisition sensor. Laboratory and field tests were performed to evaluate the data acquisition performance of the developed wireless sensor. The sensor‟s wireless immunity to interference performance was also evaluated in laboratory and field tests. The literature survey reviews current condition monitoring practices in electrical substation environments with a focus on monitoring high voltage insulators and substation earth impedance. The data acquisition performance of the wireless sensor was tested in a laboratory using two artificially polluted insulators, in a fog chamber that applied clean fog. Analysis of the test results were found to be in good agreement with those recorded directly through a data acquisition card and transmitted via coaxial cable. The wireless impedance measurement of a 275kV transmission earth tower base field test was also performed and was found to be in agreement with previous published results from standard earth measurements. The sensor‟s wireless interference performance was evaluated at a field test site when no high voltage experiments were taking place. The sensors wireless interference performance was then tested in a laboratory environment before and during high voltage tests taking place. The results of these tests were compared to each other and to published results. These tests demonstrate the suitability of the sensor‟s design and its immunity to interference. The experimental work conducted using the developed wireless sensor has led to an understanding that continuous wireless data acquisition is possible in high voltage environments. However, novel condition monitoring systems that make use of such wireless sensors, have to take into account data losses and delays adequately. Furthermore, a solar power source was designed and constructed to be used for outdoor substation applications and the solar battery charging performance of the wireless sensor was tested in a solar laboratory.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

    Multi-channel ultra-low-power receiver architecture for body area networks

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    Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 85-91).In recently published integrated medical monitoring systems, a common thread is the high power consumption of the radio compared to the other system components. This observation is indicative of a natural place to attempt a reduction in system power. Narrowband receivers in-particular can enjoy significant power reduction by employing high-Q bulk acoustic resonators as channel select filters directly at RF, allowing down-stream analog processing to be simplified, resulting in better energy efficiency. But for communications in the ISM bands, it is important to employ multiple frequency channels to permit frequency-division-multiplexing and provide frequency diversity in the face of narrowband interferers. The high-Q nature of the resonators means that frequency tuning to other channels in the same band is nearly impossible; hence, a new architecture is required to address this challenge. A multi-channel ultra-low power OOK receiver for Body Area Networks (BANs) has been designed and tested. The receiver multiplexes three Film Bulk Acoustic Resonators (FBARs) to provide three channels of frequency discrimination, while at the same time offering competitive sensitivity and superior energy efficiency in this class of BAN receivers. The high-Q parallel resonance of each resonator determines the passband. The resonator's Q is on the order of 1000 and its center frequency is approximately 2.5 GHz, resulting in a -3 dB bandwidth of roughly 2.5 MHz with a very steep rolloff. Channels are selected by enabling the corresponding LNA and mixer pathway with switches, but a key benefit of this architecture is that the switches are not in series with the resonator and do not de-Q the resonance. The measured 1E-3 sensitivity is -64 dBm at 1 Mbps for an energy efficiency of 180 pJ/bit. The resonators are packaged beside the CMOS using wirebonds for the prototype.by Phillip Michel Nadeau.S.M

    A wireless 802.11 condition monitoring sensor for electrical substation environments

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    The work reported in this thesis is concerned with the design, development and testing of a wireless 802.11 condition monitoring sensor for an electrical substation environments. The work includes a comprehensive literature review and the design and development of a novel continuous wireless data acquisition sensor. Laboratory and field tests were performed to evaluate the data acquisition performance of the developed wireless sensor. The sensor‟s wireless immunity to interference performance was also evaluated in laboratory and field tests. The literature survey reviews current condition monitoring practices in electrical substation environments with a focus on monitoring high voltage insulators and substation earth impedance. The data acquisition performance of the wireless sensor was tested in a laboratory using two artificially polluted insulators, in a fog chamber that applied clean fog. Analysis of the test results were found to be in good agreement with those recorded directly through a data acquisition card and transmitted via coaxial cable. The wireless impedance measurement of a 275kV transmission earth tower base field test was also performed and was found to be in agreement with previous published results from standard earth measurements. The sensor‟s wireless interference performance was evaluated at a field test site when no high voltage experiments were taking place. The sensors wireless interference performance was then tested in a laboratory environment before and during high voltage tests taking place. The results of these tests were compared to each other and to published results. These tests demonstrate the suitability of the sensor‟s design and its immunity to interference. The experimental work conducted using the developed wireless sensor has led to an understanding that continuous wireless data acquisition is possible in high voltage environments. However, novel condition monitoring systems that make use of such wireless sensors, have to take into account data losses and delays adequately. Furthermore, a solar power source was designed and constructed to be used for outdoor substation applications and the solar battery charging performance of the wireless sensor was tested in a solar laboratory

    Ultra-Low Power Transmitter and Power Management for Internet-of-Things Devices

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    Two of the most critical components in an Internet-of-Things (IoT) sensing and transmitting node are the power management unit (PMU) and the wireless transmitter (Tx). The desire for longer intervals between battery replacements or a completely self-contained, battery-less operation via energy harvesting transducers and circuits in IoT nodes demands highly efficient integrated circuits. This dissertation addresses the challenge of designing and implementing power management and Tx circuits with ultra-low power consumption to enable such efficient operation. The first part of the dissertation focuses on the study and design of power management circuits for IoT nodes. This opening portion elaborates on two different areas of the power management field: Firstly, a low-complexity, SPICE-based model for general low dropout (LDO) regulators is demonstrated. The model aims to reduce the stress and computation times in the final stages of simulation and verification of Systems-on-Chip (SoC), including IoT nodes, that employ large numbers of LDOs. Secondly, the implementation of an efficient PMU for an energy harvesting system based on a thermoelectric generator transducer is discussed. The PMU includes a first-in-its-class LDO with programmable supply noise rejection for localized improvement in the suppression. The second part of the dissertation addresses the challenge of designing an ultra- low power wireless FSK Tx in the 900 MHz ISM band. To reduce the power consumption and boost the Tx energy efficiency, a novel delay cell exploiting current reuse is used in a ring-oscillator employed as the local oscillator generator scheme. In combination with an edge-combiner PA, the Tx showed a measured energy efficiency of 0.2 nJ/bit and a normalized energy efficiency of 3.1 nJ/(bit∙mW) when operating at output power levels up to -10 dBm and data rates of 3 Mbps. To close this dissertation, the implementation of a supply-noise tolerant BiCMOS ring-oscillator is discussed. The combination of a passive, high-pass feedforward path from the supply to critical nodes in the selected delay cell and a low cost LDO allow the oscillator to exhibit power supply noise rejection levels better than –33 dB in experimental results
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