A Hardware Implementation of Artificial Neural Network Using Field Programmable Gate Arrays

An artificial neural network algorithm is implemented using a field programmable gate array hardware. One hidden layer is used in the feed-forward neural network structure in order to discriminate one class of patterns from the other class in real time. With five 8-bit input patterns, six hidden nodes, and one 8-bit output, the implemented hardware neural network makes decision on a set of input patterns in 11 clocks and the result is identical to what to expect from off-line computation. This implementation may be used in level 1 hardware triggers in high energy physics experimentsComment: 13 pages, 4 figures, submitted to Nucl. Instr. Meth.

Computing unite of a mobile computer vision system

The work is devoted to the computing unite of a mobile computer vision system and developing his algorithmic software. We developed hardware-implemented the convolutional neural networks on a field programmable gate array. A study of the performance and power consumption of variants of the computing unite

Energy-Efficient Inference Accelerator for Memory-Augmented Neural Networks on an FPGA

Memory-augmented neural networks (MANNs) are designed for question-answering tasks. It is difficult to run a MANN effectively on accelerators designed for other neural networks (NNs), in particular on mobile devices, because MANNs require recurrent data paths and various types of operations related to external memory access. We implement an accelerator for MANNs on a field-programmable gate array (FPGA) based on a data flow architecture. Inference times are also reduced by inference thresholding, which is a data-based maximum inner-product search specialized for natural language tasks. Measurements on the bAbI data show that the energy efficiency of the accelerator (FLOPS/kJ) was higher than that of an NVIDIA TITAN V GPU by a factor of about 125, increasing to 140 with inference thresholdingComment: Accepted to DATE 201

FPGA Implementation of Neural Nets

The field programmable gate array (FPGA) is used to build an artificial neural network in hardware. Architecture for a digital system is devised to execute a feed-forward multilayer neural network. ANN and CNN are very commonly used architectures. Verilog is utilized to describe the designed architecture. For the computation of certain tasks, a neural network\u27s distributed architecture structure makes it potentially efficient. The same features make neural nets suitable for application in VLSI technology. For the hardware of a neural network, a single neuron must be effectively implemented (NN). Reprogrammable computer systems based on FPGAs are useful for hardware implementations of neural networks

FPGA Implementation of Neural Nets

The field programmable gate array (FPGA) is used to build an artificial neural network in hardware. Architecture for a digital system is devised to execute a feed-forward multilayer neural network. ANN and CNN are very commonly used architectures. Verilog is utilized to describe the designed architecture. For the computation of certain tasks, a neural network's distributed architecture structure makes it potentially efficient. The same features make neural nets suitable for application in VLSI technology. For the hardware of a neural network, a single neuron must be effectively implemented (NN). Reprogrammable computer systems based on FPGAs are useful for hardware implementations of neural networks

In vivo measurements with a 64-channel extracellular neural recording integrated circuit

This paper presents in vivo measurements obtained from an implantable 64-channel neural recording Application Specific Integrated Circuit (ASIC) developed at IMSE and gives details of the computer interface used for real-time data acquisition. This interface connects the ASIC to a conventional 2.0 USB port by means of a Field Programmable Gate Array (FPGA). Communications are bidirectional and employ custom protocols both for delivering commands to the ASIC and for recording neural information under different channel selection and operation modes. The link is controlled by a user-friendly programming interface written in C++ which includes a built-in routine to efficiently index and store the captured data. Measurements demonstrate the suitability of the ASIC for capturing local field and action potentials with two different microelectrode array platforms.Ministerio de Economía y Competitividad TEC2012-3363