Small Form Factor Hybrid CMOS/GaN Buck Converters for 10W Point of Load Applications

abstract: Point of Load (PoL) converters are important components to the power distribution system in computer power supplies as well as automotive, space, nuclear, and medical electronics. These converters often require high output current capability, low form factor, and high conversion ratios (step-down) without sacrificing converter efficiency. This work presents hybrid silicon/gallium nitride (CMOS/GaN) power converter architectures as a solution for high-current, small form-factor PoL converters. The presented topologies use discrete GaN power devices and CMOS integrated drivers and controller loop. The presented power converters operate in the tens of MHz range to reduce the form factor by reducing the size of the off-chip passive inductor and capacitor. Higher conversion ratio is achieved through a fast control loop and the use of GaN power devices that exhibit low parasitic gate capacitance and minimize pulse swallowing. This work compares three discrete buck power converter architectures: single-stage, multi-phase with 2 phases, and stacked-interleaved, using components-off-the-shelf (COTS). Each of the implemented power converters achieves over 80% peak efficiency with switching speeds up-to 10MHz for high conversion ratio from 24V input to 5V output and maximum load current of 10A. The performance of the three architectures is compared in open loop and closed loop configurations with respect to efficiency, output voltage ripple, and power stage form factor. Additionally, this work presents an integrated CMOS gate driver solution in CMOS 0.35um technology. The CMOS integrated circuit (IC) includes the gate driver and the closed loop controller for directly driving a single-stage GaN architecture. The designed IC efficiently drives the GaN devices up to 20MHz switching speeds. The presented controller technique uses voltage mode control with an innovative cascode driver architecture to allow a 3.3V CMOS devices to effectively drive GaN devices that require 5V gate signal swing. Furthermore, the designed power converter is expected to operate under 400MRad of total dose, thus enabling its use in high-radiation environments for the large hadron collider at CERN and nuclear facilities.Dissertation/ThesisMasters Thesis Electrical Engineering 201

Improved Accuracy Area Efficient Hybrid CMOS/GaN DC-DC Buck Converterfor High Step-Down Ratio Applications

abstract: Point of Load (POL) DC-DC converters are increasingly used in space applications, data centres, electric vehicles, portable computers and devices and medical electronics. Heavy computing and processing capabilities of the modern devices have ushered the use of higher battery supply voltage to increase power storage. The need to address this consumer experience driven requirement has propelled the evolution of the next generation of small form-factor power converters which can operate with higher step down ratios while supplying heavy continuous load currents without sacrificing efficiency. Constant On-Time (COT) converter topology is capable of achieving stable operation at high conversion ratio with minimum off-chip components and small silicon area. This work proposes a Constant On-Time buck dc-dc converter for a wide dynamic input range and load currents from 100mA to 10A. Accuracy of this ripple based converter is improved by a unique voltage positioning technique which modulates the reference voltage to lower the average ripple profile close to the nominal output. Adaptive On-time block features a transient enhancement scheme to assist in faster voltage droop recovery when the output voltage dips below a defined threshold. UtilizingGallium Nitride (GaN) power switches enable the proposed converter to achieve very high efficiency while using smaller size inductor-capacitor (LC) power-stage. Use of novel Superjunction devices with higher drain-source blocking voltage simplifies the complex driver design and enables faster frequency of operation. It allows 1.8VComplementary Metal-Oxide Semiconductor (CMOS) devices to effectively drive GaNpower FETs which require 5V gate signal swing. The presented controller circuit uses internal ripple generation which reduces reliance on output cap equivalent series resistance (ESR) for loop stability and facilitates ripples reduction at the output. The ripple generation network is designed to provide ai optimally stable performance while maintaining load regulation and line regulation accuracy withing specified margin. The chip with ts external Power FET package is proposed to be integrated on a printed circuit board for testing. The designed power converter is expected to operate under 200 MRad of a total ionising dose of radiation enabling it to function within large hadron collider at CERN and space satellite and probe missions.Dissertation/ThesisMasters Thesis Electrical Engineering 201

Study and design of topologies and components for high power density DC-DC converters

Size reduction of low power electronic DC–DC converters is a topic of major interest for power electronics which requires the study and design of circuits and components working under redefined requirements. For this purpose, novel circuital topologies provide advantages in terms of power density increment, especially where a single chip design is feasible. These concepts have been applied to design and implement an integrated high step-down multiphase buck converter and to study the miniaturization of a stackable fiflyback architecture. Particular attention has been dedicated to power inductors, focusing on the modeling and measurement of magnetic materials’ hysteresis and core losses

System Identification, Diagnosis, and Built-In Self-Test of High Switching Frequency DC-DC Converters

abstract: Complex electronic systems include multiple power domains and drastically varying dynamic power consumption patterns, requiring the use of multiple power conversion and regulation units. High frequency switching converters have been gaining prominence in the DC-DC converter market due to smaller solution size (higher power density) and higher efficiency. As the filter components become smaller in value and size, they are unfortunately also subject to higher process variations and worse degradation profiles jeopardizing stable operation of the power supply. This dissertation presents techniques to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation. A digital pseudo-noise (PN) based stimulus is used to excite the DC-DC system at various circuit nodes to calculate the corresponding closed-loop impulse response. The test signal energy is spread over a wide bandwidth and the signal analysis is achieved by correlating the PN input sequence with the disturbed output generated, thereby accumulating the desired behavior over time. A mixed-signal cross-correlation circuit is used to derive on-chip impulse responses, with smaller memory and lower computational requirement in comparison to a digital correlator approach. Model reference based parametric and non-parametric techniques are discussed to analyze the impulse response results in both time and frequency domain. The proposed techniques can extract open-loop phase margin and closed-loop unity-gain frequency within 5.2% and 4.1% error, respectively, for the load current range of 30-200mA. Converter parameters such as natural frequency (ω_n ), quality factor (Q), and center frequency (ω_c ) can be estimated within 3.6%, 4.7%, and 3.8% error respectively, over load inductance of 4.7-10.3µH, and filter capacitance of 200-400nF. A 5-MHz switching frequency, 5-8.125V input voltage range, voltage-mode controlled DC-DC buck converter is designed for the proposed built-in self-test (BIST) analysis. The converter output voltage range is 3.3-5V and the supported maximum load current is 450mA. The peak efficiency of the converter is 87.93%. The proposed converter is fabricated on a 0.6µm 6-layer-metal Silicon-On-Insulator (SOI) technology with a die area of 9mm^2 . The area impact due to the system identification blocks including related I/O structures is 3.8% and they consume 530µA quiescent current during operation.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Analysis And Design Optimization Of Multiphase Converter

Future microprocessors pose many challenges to the power conversion techniques. Multiphase synchronous buck converters have been widely used in high current low voltage microprocessor application. Design optimization needs to be carefully carried out with pushing the envelope specification and ever increasing concentration towards power saving features. In this work, attention has been focused on dynamic aspects of multiphase synchronous buck design. The power related issues and optimizations have been comprehensively investigated in this paper. In the first chapter, multiphase DC-DC conversion is presented with background application. Adaptive voltage positioning and various nonlinear control schemes are evaluated. Design optimization are presented to achieve best static efficiency over the entire load range. Power loss analysis from various operation modes and driver IC definition are studied thoroughly to better understand the loss terms and minimize the power loss. Load adaptive control is then proposed together with parametric optimization to achieve optimum efficiency figure. New nonlinear control schemes are proposed to improve the transient response, i.e. load engage and load release responses, of the multiphase VR in low frequency repetitive transient. Drop phase optimization and PWM transition from long tri-state phase are presented to improve the smoothness and robustness of the VR in mode transition. During high frequency repetitive transient, the control loop should be optimized and nonlinear loop should be turned off. Dynamic current sharing are thoroughly studied in chapter 4. The output impedance of the multiphase v synchronous buck are derived to assist the analysis. Beat frequency is studied and mitigated by proposing load frequency detection scheme by turning OFF the nonlinear loop and introducing current protection in the control loop. Dynamic voltage scaling (DVS) is now used in modern Multi-Core processor (MCP) and multiprocessor System-on-Chip (MPSoC) to reduce operational voltage under light load condition. With the aggressive motivation to boost dynamic power efficiency, the design specification of voltage transition (dv/dt) for the DVS is pushing the physical limitation of the multiphase converter design and the component stress as well. In this paper, the operation modes and modes transition during dynamic voltage transition are illustrated. Critical dead-times of driver IC design and system dynamics are first studied and then optimized. The excessive stress on the control MOSFET which increases the reliability concern is captured in boost mode operation. Feasible solutions are also proposed and verified by both simulation and experiment results. CdV/dt compensation for removing the AVP effect and novel nonlinear control scheme for smooth transition are proposed for dealing with fast voltage positioning. Optimum phase number control during dynamic voltage transition is also proposed and triggered by voltage identification (VID) delta to further reduce the dynamic loss. The proposed schemes are experimentally verified in a 200 W six phase synchronous buck converter. Finally, the work is concluded. The references are listed

Analysis and design of a dual series-resonant DC-DC converter

DC-DC conversion systems are vital components in DC distribution systems, renewable energy generation systems, telecommunication systems, and portable electronics devices. The extensive applications of DC-DC converter have resulted in continuous improvement in the topologies and control methods in these converters. The challenge is to build a converter that improves factors such as efficiency of conversion and power density with a simple topology, which incorporates simplified switching and control schemes and fewer numbers of active and passive components to reduce the manufacturing cost. This thesis addresses this challenge by proposing an alternative topology of a DC-DC converter based on dual series-resonant circuits. The proposed topology operates under zero voltage switching (ZVS) and zero current switching (ZCS) conditions to reduce the switching losses. It achieves two degrees of freedom (i.e., duty ratio and switching frequency) to control the output voltage of the converter, which results in both step-down and step-up voltage conversions. The number of active components is limited to two semiconductor switches and two rectifying diodes, which reduces the manufacturing cost of the converter. Detailed analytical analysis is carried out using the extended describing function methodology to characterize the steady state and small signal operation of the converter. Small-signal transfer functions are developed and used to propose a simple closed-loop control scheme to control the output voltage of the converter. An experimental 10 V, 40 W prototype of the proposed converter is built and tested to investigate its operation and confirm its features. The improvement in the efficiency of the converter and power transfer capability of the proposed dual series-resonant converter compared with the traditional single series-resonant circuit, which is used in the interleaved topologies are experimentally verified. In addition, soft switching operation of the converter is realized and a simple control scheme is developed to control the output voltage of the converter. A detailed and step-by-step design procedure is developed, which can be used to customize the design of the converter for different levels of power and voltage. It is shown that the proposed dual series-resonant DC-DC converter provides significant improvement regarding power density, efficiency of power conversion, simplicity of switching and control schemes, and reduced number of converter components resulting in a low cost and compact converter

縦型ボディチャネルMOS Field-Effect Transistorを用いたマイクロプロセッサ向け高効率・高集積DC-DCコンバータとそのパワーマネジメントに関する研究

Tohoku University遠藤哲郎課

Pushing the Boundary of the 48 V Data Center Power Conversion in the AI and IoT Era

openThe increasing interest in cloud-based services, the Internet-of-Things and the take-over of artificial intelligence computing require constant improvement of the power distribution network. Electricity consumption of data centers, which drains a consistent slice of modern world energy production, is projected to increase tremendously during the next decade. Data centers are the backbone of modern economy; as a consequence, energy-aware resource allocation heuristics are constantly researched, leading the major IT services providers to develop new power conversion architectures to increase the overall webfarm distribution efficiency, together reducing the resulting carbon footprint and maximizing their investments. As higher voltage distribution yields lower conduction losses, vendors are moving from the 12 V rack bus to 48 V solutions together with research centers and especially data center developers. As mentioned, efficiency is crucial to address in this scenario and the whole conversion chain, i.e. from the 48 V bus to the CPU/GPU/ASIC voltage, must be optimized to decrease wasted energy inside the server rack. Power density for this converters family is also paramount to consider, as the overall system must occupy as less area and volume as possible. LLC resonant converters are commonly used as IBCs (intermediate bus converters), together with their GaN implementations because of their multiple advantages in efficiency and size, while multiphase-buck-derived topologies are the most common solution to step-down-to and regulate the final processor voltage as they're well-know, easy to scale and design. This dissertation proposes a family of non-isolated, innovative converters capable of increasing the power density and the efficiency of the state-of-the-art 48 V to 1.8/0.9 V conversion. In this work three solutions are proposed, which can be combined or used as stand-alone converters: an ASIC on-chip switched-capacitor resonant voltage divider, two unregulated Google-STC-derived topologies for the IBC stage (48 V to 12 V and 48 V to 4.8 V + 10.6 V dual-output) and a complete 48 V to 1.8 V ultra-dense PoL converter. Each block has been thoroughly tested and researched, therefore mathematical and experimental results are provided for each solution, together with state-of-the-art comparisons and contextualization.The increasing interest in cloud-based services, the Internet-of-Things and the take-over of artificial intelligence computing require constant improvement of the power distribution network. Electricity consumption of data centers, which drains a consistent slice of modern world energy production, is projected to increase tremendously during the next decade. Data centers are the backbone of modern economy; as a consequence, energy-aware resource allocation heuristics are constantly researched, leading the major IT services providers to develop new power conversion architectures to increase the overall webfarm distribution efficiency, together reducing the resulting carbon footprint and maximizing their investments. As higher voltage distribution yields lower conduction losses, vendors are moving from the 12 V rack bus to 48 V solutions together with research centers and especially data center developers. As mentioned, efficiency is crucial to address in this scenario and the whole conversion chain, i.e. from the 48 V bus to the CPU/GPU/ASIC voltage, must be optimized to decrease wasted energy inside the server rack. Power density for this converters family is also paramount to consider, as the overall system must occupy as less area and volume as possible. LLC resonant converters are commonly used as IBCs (intermediate bus converters), together with their GaN implementations because of their multiple advantages in efficiency and size, while multiphase-buck-derived topologies are the most common solution to step-down-to and regulate the final processor voltage as they're well-know, easy to scale and design. This dissertation proposes a family of non-isolated, innovative converters capable of increasing the power density and the efficiency of the state-of-the-art 48 V to 1.8/0.9 V conversion. In this work three solutions are proposed, which can be combined or used as stand-alone converters: an ASIC on-chip switched-capacitor resonant voltage divider, two unregulated Google-STC-derived topologies for the IBC stage (48 V to 12 V and 48 V to 4.8 V + 10.6 V dual-output) and a complete 48 V to 1.8 V ultra-dense PoL converter. Each block has been thoroughly tested and researched, therefore mathematical and experimental results are provided for each solution, together with state-of-the-art comparisons and contextualization.Dottorato di ricerca in Ingegneria industriale e dell'informazioneopenUrsino, Mari

Merged Two-Stage Power Converter With Soft Charging Switched-Capacitor Stage in 180 nm CMOS

In this paper, we introduce a merged two-stage dc-dc power converter for low-voltage power delivery. By separating the transformation and regulation function of a dc-dc power converter into two stages, both large voltage transformation and high switching frequency can be achieved. We show how the switched-capacitor stage can operate under soft charging conditions by suitable control and integration (merging) of the two stages. This mode of operation enables improved efficiency and/or power density in the switched-capacitor stage. A 5-to-1 V, 0.8 W integrated dc-dc converter has been developed in 180 nm CMOS. The converter achieves a peak efficiency of 81%, with a regulation stage switching frequency of 10 MHz.Interconnect Focus Center (United States. Defense Advanced Research Projects Agency and Semiconductor Research Corporation