Spur-reduced digital sinusoid synthesis

This article presents and analyzes a technique for reducing the spurious signal content in digital sinusoid synthesis. Spurious-harmonic (spur) reduction is accomplished through dithering both amplitude and phase values prior to word-length reduction. The analytical approach developed for analog quantization is used to produce new bounds on spur performance in these dithered systems. Amplitude dithering allows output word-length reduction without introducing additional spurs. Effects of periodic dither similar to those produced by a pseudonoise (PN) generator are analyzed. This phase-dithering method provides a spur reduction of 6(M plus one) dB per phase bit when the dither consists of M uniform variates. While the spur reduction is at the expense of an increase in system noise, the noise power can be made white, making the power spectral density small. This technique permits the use of a smaller number of phase bits addressing sinusoid lookup tables, resulting in an exponential decrease in system complexity. Amplitude dithering allows the use of less complicated multipliers and narrower data paths in purely digital applications, as well as the use of coarse resolution, highly linear digital to analog converters (DAC's) to obtain spur performance limited by the DAC linearity rather than its resolution

Hardware Implementation of 32-Bit High-Speed Direct Digital Frequency Synthesizer

The design and implementation of a high-speed direct digital frequency synthesizer are presented. A modified Brent-Kung parallel adder is combined with pipelining technique to improve the speed of the system. A gated clock technique is proposed to reduce the number of registers in the phase accumulator design. The quarter wave symmetry technique is used to store only one quarter of the sine wave. The ROM lookup table (LUT) is partitioned into three 4-bit sub-ROMs based on angular decomposition technique and trigonometric identity. Exploiting the advantages of sine-cosine symmetrical attributes together with XOR logic gates, one sub-ROM block can be removed from the design. These techniques, compressed the ROM into 368 bits. The ROM compressed ratio is 534.2 : 1, with only two adders, two multipliers, and XOR-gates with high frequency resolution of 0.029 Hz. These techniques make the direct digital frequency synthesizer an attractive candidate for wireless communication applications

Tutorial on direct digital synthesizer structure improvements and static timing analysis

The direct digital frequency synthesizer (DDS) has been widely used in digital communication systems due to its high frequency resolution, fast frequency conversion, and continuous phase change. With the development of microelectronics technology, field-programmable gate array (FPGA) devices have been rapidly developed. Because of FPGAs’ high speed, high integration and field-programmable advantages, the devices are widely used in digital processing and are increasingly favored by hardware circuit design engineers. FPGAs also provide a technique for using digital data processing blocks as a means to generate a frequency and phase tunable output signal referenced to a fixed-frequency precision clock source. Many telecommunication applications require such high-speed switching, fine tunability and superior quality signal source for their components. This thesis will introduce the direct digital synthesizer (DDS) and investigate some ways to optimize the DDS structure to save hardware resources and increase chip speed without sacrificing signal quality. The Verilog hardware description language is used as the development language. This thesis will describe entire designs of both DDS with traditional structure and DDS with new structures. By comparing the outputs, it also examines the corresponding simulation results and verifies the improvement of the signal quality

The Telecommunications and Data Acquisition Report

This quarterly publication provides archival reports on developments in programs managed by JPL's Office of Telecommunications and Data Acquisition (TDA). In space communications, radio navigation, radio science, and ground-based radio and radar astronomy, it reports on activities of the Deep Space Network (DSN) in planning, supporting research and technology, implementation, and operations. Also included are standards activity at JPL for space data and information systems and reimbursable DSN work performed for other space agencies through NASA. The papers included in this document cover satellite tracking and ground-based navigation, spacecraft-ground communications, and optical communication systems for the Deep Space Network

Ein Beitrag zur Modellierung und Realisierung der direkten digitalen Frequenzsynthese

In der Dissertationsschrift wird ein neuartiges Konzept der Realisierung der Direkten Digitalen Frequenzsynthese (DDS) vorgestellt. Ausgehend von der analysierten Literatur werden das Wirkprinzip eines Standard-DDS-Synthesizer analysiert und Möglichkeiten zur Aufwandsreduktion untersucht. Ein neuartiger Ansatz zur Realisierung einer vollständig digitalen DDS ergibt sich in der Anwendung der Pulse-Output-DDS. Bei der Pulse-Output-DDS wird neben dem D/A-Wandler auch die Sinus-ROM-Tabelle aus dem prinzipiellen Aufbau der Standard-DDS entfernt. Ausgehend von einer derart modifizierten DDS-Struktur wird ein geeignetes DDS-Modell entwickelt, mit welchem alle auftretenden Synthesefehler systematisch erfaßt und bewertet werden können. Die gewonnenen Erkenntnisse über die prinzipbedingten Synthesefehler bilden die Grundlage für Erweiterungen der Pulse-Output-DDS mit deren Hilfe eine qualitative Verbesserung des synthetisierten Signals erreicht wird. Dabei steht vor allem die Anwendung von Verfahren der digitalen Signalverarbeitung im Vordergrund, die zu einer Verringerung bzw. Kompensation oder zu einer spektralen Veränderung des auftretenden DDS-Fehlersignals geeignet sind. Es werden die erreichbaren Verbesserungen, aber auch die theoretischen und praktischen Grenzen von folgenden Verfahren aufgezeigt: absolute Verringerung des DDS-Fehlersignals Dithering des DDS-Fehlersignals Rauschformung (Noise-Shaping) des Fehlersignalspektrums Insbesondere bei der Rauschformung werden unterschiedliche Ansätze untersucht und bewertet mit dem Ziel, ein optimales Verfahren für den Rauschformungsprozeß bei der Verwendung in einer Pulse-Output-DDS zu finden. Durch die echtzeitfähige Implementation eines erweiterten DDS-Systems in einem Standard-CMOS-Prozeß werden die gefundenen theoretischen Lösungen verifiziert