차량용 CIS Interface 를 위한 All-Digital Phase-Locked Loop 의 설계 및 분석

학위논문 (석사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2021. 2. 정덕균.This thesis presents design techniques for All-Digital Phase-Locked Loop (ADPLL) assisting the automotive CMOS image sensor (CIS) interface. To target Gear 3 of the automotive physical system, the proposed AD-PLL has a wide operation range, low RMS jitter, and high PVT tolerance characteristics. Detailed analysis of the loop dynamics and the noise analysis of AD-PLL are done by using Matlab and Verilog behavioral modeling simulation before an actual design. Based on that analysis, the optimal DLF gain configurations are yielded, and also, accurate output responses and performance are predictable. The design techniques to reduce the output RMS jitter are discussed thoroughly and utilized for actual implementation. The proposed AD-PLL is fabricated in the 40 nm CMOS process and occupies an effective area of 0.026 mm2. The PLL output clock pulses exhibit an RMS jitter of 827 fs at 2 GHz. The power dissipation is 5.8 mW at 2 GHz, where the overall supply voltage domain is 0.9 V excluding the buffer which is 1.1 V domain.본 논문에서는 자동차 CMOS 이미지 센서 (CIS) 인터페이스를 지원하 는 AD-PLL 을 제안한다. Automotive Physical 시스템의 Gear 3 를 지원하기 위해 제안된 AD-PLL 은 1.5 GHz 에서 3 GHz 의 동작 주파수를 가지며, 낮 은 RMS Jitter 및 PVT 변화에 대한 높은 둔감성을 갖는다. 설계에 앞서서 Matlab 및 Verilog Behavioral Simulation 을 통해 Loop system 의 역학에 대한 자세한 분석 및 AD-PLL 의 Noise 분석을 수행하였고, 이 분석을 기반으로 최적의 DLF gain 과 정확한 출력 응답 및 성능을 예측 할 수 있었다. 또한, 출력의 Phase Noise 와 RMS Jitter 를 줄이기 위한 설계 기법을 자세히 다루고 있으며 이를 실제 구현에 활용했다. 제안된 회로는 40 nm CMOS 공정으로 제작되었으며 Decoupling Cap 을 제외하고 0.026 mm2 의 유효 면적을 차지한다. 측정된 출력 Clock 신호의 RMS Jitter 값은 2 GHz 에서 827 fs 이며, 총 5.8 mW의 Power 를 소비한다. 이 때, 전체적인 공급 전압은 0.9 V 이며, Buffer 의 Power 만이 1.1 V 를 사용하 였다.ABSTRACT I CONTENTS II LIST OF FIGURES IV LIST OF TABLES VII CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 3 CHAPTER 2 BACKGROUND ON ALL-DIGITAL PLL 4 2.1 OVERVIEW 4 2.2 BUILDING BLOCKS OF AD-PLL 7 2.2.1 TIME-TO-DIGITAL CONVERTER 7 2.2.2 DIGITALLY-CONTROLLED OSCILLATOR 10 2.2.3 DIGITAL LOOP FILTER 13 2.2.4 DELTA-SIGMA MODULATOR 16 2.3 PHASE NOISE ANALYSIS OF AD-PLL 20 2.3.1 BASIC ASSUMPTION OF LINEAR ANALYSIS 20 2.3.2 NOISE SOURCES OF AD-PLL 21 2.3.3 EFFECTS OF LOOP DELAY ON AD-PLL 24 2.3.4 PHASE NOISE ANALYSIS OF PROPOSED AD-PLL 26 CHAPTER 3 DESIGN OF ALL-DIGITAL PLL 28 3.1 DESIGN CONSIDERATION 28 3.2 OVERALL ARCHITECTURE 30 3.3 CIRCUIT IMPLEMENTATION 32 3.3.1 PFD-TDC 32 3.3.2 DCO 37 3.3.3 DIGITAL BLOCK 43 3.3.4 LEVEL SHIFTING BUFFER AND DIVIDER 45 CHAPTER 4 MEASUREMENT AND SIMULATION RESULTS 52 4.1 DIE PHOTOMICROGRAPH 52 4.2 MEASUREMENT SETUP 54 4.3 TRANSIENT ANALYSIS 57 4.4 PHASE NOISE AND SPUR PERFORMANCE 59 4.4.1 FREE-RUNNING DCO 59 4.4.2 PLL PERFORMANCE 61 4.5 PERFORMANCE SUMMARY 65 CHAPTER 5 CONCLUSION 67 BIBLIOGRAPHY 68 초 록 72Maste

다이렉트 경로를 이용한 5/8GHz 듀얼 모드 All-Digital Phase-Locked Loop의 설계

학위논문 (석사)-- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2019. 2. 정덕균.최근 데이터의 전송 속도가 비약적으로 증가함에 따라 데이터 처리 방식이 다양하게 연구되었고 여러 방식에 따른 고속의 송수신기 설계가 중요시되고 있다. 그 중에서도 Clock 신호를 합성하는 역할인 Phase-Locked Loop (PLL)에 대한 연구가 활발히 진행되고 있다. 특히 패시브 소자를 Loop Filter에 사용해야 하는 Analog PLL보다는 PVT 변화에 둔감하고 Programmable 하다는 장점을 가진 All Digital PLL (AD-PLL)에 대한 관심도가 높아지고 있다. 본 논문에서는 Peripheral Component Interconnect Express Memory interface (PCIe) 지원을 위한 32Gbps Serial Link에 Common Clock 신호를 제공하는 5/8 GHz 듀얼 모드 AD-PLL을 제안한다. 이전 세대와의 호환성을 위해 넓은 동작 영역을 갖고 모드 선택이 가능한 듀얼 모드 Digitally Controlled Oscillator (DCO)를 사용하였고 설계 전 Digital 방식으로 변환함에 따라 발생하는 Quantization Noise에 대해 분석하고 Matlab, Verilog Behavioral Simulation을 통해 출력의 Phase Noise와 RMS Jitter 값을 예측해 볼 수 있었다. 또한 Reference Clock의 한 주기 이내에 정보가 Update되지 못하는 Loop Delay의 문제를 해결하기 위해 Digital Loop Filter (DLF)의 처리 과정을 거치지 않고 Time to Digital Converter (TDC)의 출력을 DCO에 바로 전달해 줄 수 있는 다이렉트 경로를 제안하였다. 설계된 회로는 TSMC 사의 65nm 공정으로 구현되었고 AD-PLL의 전체 유효 면적은 Decoupling Cap을 제외하고 420um·300um이며 측정된 출력 Clock 신호의 RMS Jitter값은 8GHz 모드에서 357fs, 5GHz 모드에서 394fs이다. AD-PLL의 동작 주파수는 PCIe Spec의 다양한 모드를 지원하기 위해 외부의 입력 모드 신호에 따라서 5GHz/8GHz의 High/Low Band를 지원하고 1.2V의 공급 전압에서 Repeater를 제외하고 8GHz 모드에서는 총 18.26mW, 5GHz 모드에서는 총 12.06mW의 Power를 소비한다.As data transmission speed has increased in recent years, a variety of data processing techniques have been studied and high-speed transceiver has become important. Above all, Phase-Locked Loop (PLL), which synthesizes high frequency clock signal, is one of the important parts. In particular, All-Digital PLL(AD-PLL), which has advantage of programmability and PVT tolerance, is replacing Analog PLL that requires passive element utilization. This thesis presents a 5/8GHz dual mode AD-PLL to provide common clock signal to 32Gbps serial link to support Peripheral Component Interconnect Express(PCIe) PHY. For compatibility with previous generations and wide operating region, AD-PLL uses dual mode Digitally Controlled Oscillator(DCO). Before an actual design, output RMS Jitter, Phase Noise of AD-PLL and quantization error resulting from digital conversion are calculated and analyzed by using Matlab, Verilog behavioral simulation in a short time. In addition, the output of Time-to-Digital Converter(TDC) is directly delivered to the DCO without Digital Loop Filter(DLF) using direct path to solve loop delay issue where information cant be updated within a cycle of reference clock. The proposed AD-PLL is fabricated in 65nm CMOS process and effective area of AD-PLL is 420um·300um and the measured RMS Jitter is 357fs at 8GHz mode, 394fs at 5GHz mode. Also, proposed AD-PLL supports the low/high band(5/8GHz) to be compatible with the various modes of PCIe spec. Power dissipation is 18.26mW at 8GHz mode, 12.06mW at 5GHz mode in 1.2V supply voltage domain excluding repeater.제 1 장 서 론 1 1.1 연구의 배경 1 1.2 논문의 구성 3 제 2 장 Basics of AD-PLL 4 2.1 Introduction of AD-PLL 4 2.2 Building Blocks of AD-PLL 5 2.2.1 Time to Digital Converter 6 2.2.2 Digital Loop Filter 8 2.2.3 Digitally Controlled Oscillator 10 2.3 Phase Noise Analysis 13 2.4 Loop Delay 18 제 3 장 Design of AD-PLL 22 3.1 Design Consideration 22 3.2 Overall Architecture 22 3.3 Phase Frequency Detectable TDC 24 3.4 Digital Loop Filter 27 3.5 Digitally Controlled Oscillator 30 3.6 Direct Path 33 3.7 Level Shifter and Divider 36 3.8 Clock Tree 39 제 4 장 Measurement and Simulation Results 41 4.1 Measurement Setup 41 4.2 Die Photomicrograph 43 4.3 Frequency Tracking Behavior 44 4.4 Clock Distribution 46 4.5 Phase Noise and Spur 47 4.6 Performance Summary 53 제 5 장 Conclusion 55 참고 문헌 56 Abstract 59Maste

저전력, 저면적 유선 송수신기 설계를 위한 회로 기술

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 8. 정덕균.In this thesis, novel circuit techniques for low-power and area-efficient wireline transceiver, including a phase-locked loop (PLL) based on a two-stage ring oscillator, a scalable voltage-mode transmitter, and a forwarded-clock (FC) receiver based on a delay-locked-loop (DLL) based per-pin deskew, are proposed. At first, a two-stage ring PLL that provides a four-phase, high-speed clock for a quarter-rate TX in order to minimize power consumption is presented. Several analyses and verification techniques, ranging from the clocking architectures for a high-speed TX to oscillation failures in a two-stage ring oscillator, are addressed in this thesis. A tri-state-inverter–based frequency-divider and an AC-coupled clock-buffer are used for high-speed operations with minimal power and area overheads. The proposed PLL fabricated in the 65-nm CMOS technology occupies an active area of 0.009 mm2 with an integrated-RMS-jitter of 414 fs from 10 kHz to 100 MHz while consuming 7.6 mW from a 1.2-V supply at 10 GHz. The resulting figure-of-merit is -238.8 dB, which surpasses that of the state-of-the-art ring-PLLs by 4 dB. Secondly, a voltage-mode (VM) transmitter which offers a wide operation range of 6 to 32 Gb/s, controllable pre-emphasis equalization and output voltage swing without altering output impedance, and a power supply scalability is presented. A quarter-rate clocking architecture is employed in order to maximize the scalability and energy efficiency across the variety of operating conditions. A P-over-N VM driver is used for CMOS compatibility and wide voltage-swing range required for various I/O standards. Two supply regulators calibrate the output impedance of the VM driver across the wide swing and pre-emphasis range. A single phase-locked loop is used to provide a wide frequency range of 1.5-to-8 GHz. The prototype chip is fabricated in 65-nm CMOS technology and occupies active area of 0.48x0.36 mm2. The proposed transmitter achieves 250-to-600-mV single-ended swing and exhibits the energy efficiency of 2.10-to-2.93 pJ/bit across the data rate of 6-to-32 Gb/s. And last, this thesis describes a power and area-efficient FC receiver and includes an analysis of the jitter tolerance of the FC receiver. In the proposed design, jitter tolerance is maximized according to the analysis by employing a DLL-based de-skewing. A sample-swapping bang-bang phase-detector (SS-BBPD) eliminates the stuck locking caused by the finite delay range of the voltage-controlled delay line (VCDL), and also reduces the required delay range of the VCDL by half. The proposed FC receiver is fabricated in 65-nm CMOS technology and occupies an active area of 0.025 mm2. At a data rate of 12.5 Gb/s, the proposed FC receiver exhibits an energy efficiency of 0.36 pJ/bit, and tolerates 1.4-UIpp sinusoidal jitter of 300 MHz.Chapter 1. Introduction 1 1.1. Motivation 1 1.2. Thesis organization 5 Chapter 2. Phase-Locked Loop Based on Two-Stage Ring Oscillator 7 2.1. Overivew 7 2.2. Background and Analysis of a Two-stage Ring Oscillator 11 2.3. Circuit Implementation of The Proposed PLL 25 2.4. Measurement Results 33 Chapter 3. A Scalable Voltage-Mode Transmitter 37 3.1. Overview 37 3.2. Design Considerations on a Scalable Serial Link Transmitter 40 3.3. Circuit Implementation 46 3.4. Measurement Results 56 Chapter 4. Delay-Locked Loop Based Forwarded-Clock Receiver 62 4.1. Overview 62 4.2. Timing and Data Recovery in a Serial Link 65 4.3. DLL-Based Forwarded-Clock Receiver Characteristics 70 4.4. Circuit Implementation 79 4.5. Measurement Results 89 Chapter 5. Conclusion 94 Appendix 96 Appendix A. Design flow to optimize a high-speed ring oscillator 96 Appendix B. Reflection Issues in N-over-N Voltage-Mode Driver 99 Appendix C. Analysis on output swing and power consumption of the P-over-N voltage-mode driver 107 Appendix D. Loop Dynamics of DLL 112 Bibliography 121 Abstract 128Docto

Digital Multiplying Delay-Locked Loop Using Switched Biasing Technique and Digital Phase-Locked Loop with Bandwidth Calibration

這篇論文的主題主要分為兩個部分，第一部分我們實現了一個數位倍頻延遲鎖定迴路搭配切換偏壓技術。我們所提出的選擇邏輯以及除頻器可關掉的架構都可以降低電路的功率消耗。使用切換偏壓技術的數位控制振盪器可以減少低頻相位雜訊，此電路實現於40奈米製程，其面積為0.0088 mm2，在1050 MHz頻率量測到的方均根抖動為2.68 ps，功率消耗為1.51 mW。 第二部分實現了一個具有頻寬校正之數位Bang-Bang鎖相迴路，此電路可以不受環境、製程變異影響，我們採用線性模型去分析此電路的頻寬。所提出的的頻寬校正電路使用數位加法器、減法器以及比較器去取代佔面積的數位除法器，達到小面積的目標。此電路實現於40奈米製程，其面積為0.0049 mm2，在5 GHz頻率量測到的方均根抖動為1.242 ps，功率消耗為3.34 mW。This thesis consists of two parts. The first part implement a digital multiplying delay-locked loop (DMDLL) using switched biasing technique. This DMDLL uses the proposed select logic and its main divider can be turned off to reduce the power consumption. The digitally-controlled oscillator (DCO) uses the switched biasing technique to reduce the low-frequency phase noise. This DMDLL is fabricated in 40-nm CMOS technology and its active area is 0.0088 mm2. The integrated RMS jitter is 2.68 ps and the power consumption is 1.51mW at the output frequency of 1050MHz. The second part implements a digital bang-bang phase-locked loop (BBPLL) with bandwidth calibration. It is presented to against the process, voltage, and temperature (PVT) variations. A linearized model of the BBPLL is constructed to analyze the bandwidth of the BBPLL. The proposed bandwidth calibration circuit adopts the adders, the subtractors, and the comparators to replace the area-consuming division circuit, which reduces the area overhead. This BBPLL was fabricated in 40-nm CMOS technology with an active area of 0.0049 mm2. The output frequency is 5 GHz. The integrated RMS jitter is 1.242 ps, and the power consumption is 3.34 mW.1. Introduction 1 1.1 Motivation 1 1.2 Overview 2 2. A Digital MDLL Using Switched Biasing Technique to Reduce Low-Frequency Phase Noise 5 2.1 Motivation 5 2.2 Circuit Description 6 2.2.1 DMDLL 6 2.2.2 S2D, Input buffers & Select Logic 8 2.2.3 BBPFD 10 2.2.4 The proposed DCO using switched biasing technique 11 2.3 Phase Noise Analysis 16 2.4 Measurement Results 19 2.5 Die Photo and Performance Summary 21 3. A Digital Bang-Bang Phase-Locked Loop with Bandwidth Calibration 23 3.1 Motivation 23 3.2 BBPLL Analysis 24 3.3 Circuit Description 28 3.3.1 Bandwidth Calibration 29 3.3.2 BBPFD and DLF 33 3.3.3 Dual-modulus divider and DCO 34 3.4 Phase Noise Analysis 35 3.5 Measurement Results 38 3.6 Die Photo and Performance Summary 41 4. Conclusion and Future Work 43 4.1 Conclusion 43 4.2 Future Work 44 Bibliography 4