Assessment of 50%-Propagation-Delay for Cascaded PCB Non-Linear Interconnect Lines for the High-Rate Signal Integrity Analysis

This paper presents an enlarged study about the 50-% propagation-time assessment of cascaded transmission lines (TLs). First and foremost, the accurate modeling and measurement technique of signal integrity (SI) for high-rate microelectronic interconnection is recalled. This model is based on the reduced transfer function extracted from the electromagnetic (EM) behavior of the interconnect line RLCG-parameters. So, the transfer function established takes into account both the frequency dispersion effects and the different propagation modes. In addition, the transfer function includes also the load and source impedance effects. Then, the SI analysis is proposed for high-speed digital signals through the developed model. To validate the model understudy, a prototype of microstrip interconnection with w = 500 µm and length d = 33 mm was designed, simulated, fabricated and tested. Then, comparisons between the frequency and time domain results from the model and from measurements are performed. As expected, good agreement between the S-parameters form measurements and the model proposed is obtained from DC to 8 GHz. Furthermore, a de-embedding method enabling to cancel out the connectors and the probe effects are also presented. In addition, an innovative time-domain characterization is proposed in order to validate the concept with a 2.38 Gbit/s-input data signal. Afterwards, the 50-% propagation-time assessment problem is clearly exposed. Consequently an extracting theory of this propagation-time with first order RC-circuits is presented. Finally, to show the relevance of this calculation, propagation-time simulations and an application to signal integrity issues are offered

Quantitative and functional post-translational modification proteomics reveals that TREPH1 plays a role in plant thigmomorphogenesis

Plants can sense both intracellular and extracellular mechanical forces and can respond through morphological changes. The signaling components responsible for mechanotransduction of the touch response are largely unknown. Here, we performed a high-throughput SILIA (stable isotope labeling in Arabidopsis)-based quantitative phosphoproteomics analysis to profile changes in protein phosphorylation resulting from 40 seconds of force stimulation in Arabidopsis thaliana. Of the 24 touch-responsive phosphopeptides identified, many were derived from kinases, phosphatases, cytoskeleton proteins, membrane proteins and ion transporters. TOUCH-REGULATED PHOSPHOPROTEIN1 (TREPH1) and MAP KINASE KINASE 2 (MKK2) and/or MKK1 became rapidly phosphorylated in touch-stimulated plants. Both TREPH1 and MKK2 are required for touch-induced delayed flowering, a major component of thigmomorphogenesis. The treph1-1 and mkk2 mutants also exhibited defects in touch-inducible gene expression. A non-phosphorylatable site-specific isoform of TREPH1 (S625A) failed to restore touch-induced flowering delay of treph1-1, indicating the necessity of S625 for TREPH1 function and providing evidence consistent with the possible functional relevance of the touch-regulated TREPH1 phosphorylation. Bioinformatic analysis and biochemical subcellular fractionation of TREPH1 protein indicate that it is a soluble protein. Altogether, these findings identify new protein players in Arabidopsis thigmomorphogenesis regulation, suggesting that protein phosphorylation may play a critical role in plant force responses

Analytic Delay Model of RLC Interconnects using Numerical Inversion of the Laplace Transform

Signal integrity analysis for on-chip interconnect becomes increasingly important in high-speed designs. SPICE, a conventional circuit simulator, can provide accurate prediction for interconnects, however, using SPICE is extremely computationally expensive. On the other hand, explicit moment matching technique can produce unstable poles for highly accurate approximations and implicit moment matching technique can obtain more accurate approximations at the expense of computational complexity. This thesis presents an analytic model to efficiently estimate the signal delays of RLC on-chip interconnects. It uses the numerical inversion of Laplace transform (NILT) to obtain time function, suitable for transient analysis. Since the integration formula of the NILT is numerically stable for higher order approximations, the developed algorithm provides a mechanism to increase the accuracy for delay estimation. Numerical examples are implemented and compared with HSPICE, two-pole model and Passive Reduced-Order Interconnect Macromodeling Algorithm (PRIMA) to illustrate the efficiency and validity of the proposed work

Concurrent optimization strategies for high-performance VLSI circuits

In the next generation of VLSI circuits, concurrent optimizations will be essential to achieve the performance challenges. In this dissertation, we present techniques for combining traditional timing optimization techniques to achieve a superior performance;The method of buffer insertion is used in timing optimization to either increase the driving power of a path in a circuit, or to isolate large capacitive loads that lie on noncritical or less critical paths. The procedure of transistor sizing selects the sizes of transistors within a circuit to achieve a given timing specification. Traditional design techniques perform these two optimizations as independent steps during synthesis, even though they are intimately linked and performing them in alternating steps is liable to lead to suboptimal solutions. The first part of this thesis presents a new approach for unifying transistor sizing with buffer insertion. Our algorithm achieve from 5% to 49% area reduction compared with the results of a standard transistor sizing algorithm;The next part of the thesis deals with the problem of collapsing gates for technology mapping. Two new techniques are proposed. The first method, the odd-level transistor replacement (OTR) method, performs technology mapping without the restriction of a fixed library size, and maps a circuit to a virtual library of complex static CMOS gates. The second technique, the Static CMOS/PTL method, uses a mix of static CMOS and pass transistor logic (PTL) to realize the circuit, using the relation between PTL and binary decision diagrams. The methods are very efficient and can handle all ISCAS\u2785 benchmark circuits in minutes. On average, it was found that the OTR method gave 40%, and the Static/PTL gave 50% delay reductions over SIS, with substantial area savings;Finally, we extend the technology mapping work to interleave it with placement in a single optimization. Conventional methods that perform these steps separately will not be adequate for next-generation circuits. Our approach presents an integrated solution to this problem, and shows an average of 28.19%, and a maximum of 78.42% improvement in the delay over a method that performs the two optimizations in separate steps

HIGH PERFORMANCE CLOCK DISTRIBUTION FOR HIGH-SPEED VLSI SYSTEMS

Tohoku University堀口 進課

Modeling and characterization of on-chip interconnects, inductors and transformers

Ph.DNUS-SUPELEC JOINT PH.D. PROGRAMM

Transient simulation of complex electronic circuits and systems operating at ultra high frequencies

The electronics industry worldwide faces increasingly difficult challenges in a bid to produce ultra-fast, reliable and inexpensive electronic devices. Electronic manufacturers rely on the Electronic Design Automation (EDA) industry to produce consistent Computer A id e d Design (CAD) simulation tools that w ill enable the design of new high-performance integrated circuits (IC), the key component of a modem electronic device. However, the continuing trend towards increasing operational frequencies and shrinking device sizes raises the question of the capability of existing circuit simulators to accurately and efficiently estimate circuit behaviour. The principle objective of this thesis is to advance the state-of-art in the transient simulation of complex electronic circuits and systems operating at ultra high frequencies. Given a set of excitations and initial conditions, the research problem involves the determination of the transient response o f a high-frequency complex electronic system consisting of linear (interconnects) and non-linear (discrete elements) parts with greatly improved efficien cy compared to existing methods and with the potential for very high accuracy in a way that permits an effective trade-off between accuracy and computational complexity. High-frequency interconnect effects are a major cause of the signal degradation encountered b y a signal propagating through linear interconnect networks in the modem IC. Therefore, the development of an interconnect model that can accurately and efficiently take into account frequency-dependent parameters of modem non-uniform interconnect is of paramount importance for state-of-art circuit simulators. Analytical models and models based on a set of tabulated data are investigated in this thesis. Two novel, h igh ly accurate and efficient interconnect simulation techniques are developed. These techniques combine model order reduction methods with either an analytical resonant model or an interconnect model generated from frequency-dependent sparameters derived from measurements or rigorous full-wave simulation. The latter part o f the thesis is concerned with envelope simulation. The complex mixture of profoundly different analog/digital parts in a modern IC gives rise to multitime signals, where a fast changing signal arising from the digital section is modulated by a slower-changing envelope signal related to the analog part. A transient analysis of such a circuit is in general very time-consuming. Therefore, specialised methods that take into account the multi-time nature o f the signal are required. To address this issue, a novel envelope simulation technique is developed. This technique combines a wavelet-based collocation method with a multi-time approach to result in a novel simulation technique that enables the desired trade-off between the required accuracy and computational efficiency in a simple and intuitive way. Furthermore, this new technique has the potential to greatly reduce the overall design cycle

Power-Aware Datacenter Networking and Optimization

Present-day datacenter networks (DCNs) are designed to achieve full bisection bandwidth in order to provide high network throughput and server agility. However, the average utilization of typical DCN infrastructure is below 10% for significant time intervals. As a result, energy is wasted during these periods. In this thesis we analyze traffic behavior of datacenter networks using traces as well as simulated models. Based on the insight developed, we present techniques to reduce energy waste by making energy use scale linearly with load. The solutions developed are analyzed via simulations, formal analysis, and prototyping. The impact of our work is significant because the energy savings we obtain for networking infrastructure of DCNs are near optimal. A key finding of our traffic analysis is that network switch ports within the DCN are grossly under-utilized. Therefore, the first solution we study is to modify the routing within the network to force most traffic to the smallest of switches. This increases the hop count for the traffic but enables the powering off of many switch ports. The exact extent of energy savings is derived and validated using simulations. An alternative strategy we explore in this context is to replace about half the switches with fewer switches that have higher port density. This has the effect of enabling even greater traffic consolidation, thus enabling even more ports to sleep. Finally, we explore a third approach in which we begin with end-to-end traffic models and incrementally build a DCN topology that is optimized for that model. In other words, the network topology is optimized for the potential use of the datacenter. This approach makes sense because, as other researchers have observed, the traffic in a datacenter is heavily dependent on the primary use of the datacenter. A second line of research we undertake is to merge traffic in the analog domain prior to feeding it to switches. This is accomplished by use of a passive device we call a merge network. Using a merge network enables us to attain linear scaling of energy use with load regardless of datacenter traffic models. The challenge in using such a device is that layer 2 and layer 3 protocols require a one-to-one mapping of hardware addresses to IP (Internet Protocol) addresses. We overcome this problem by building a software shim layer that hides the fact that traffic is being merged. In order to validate the idea of a merge network, we build a simple mere network for gigabit optical interfaces and demonstrate correct operation at line speeds of layer 2 and layer 3 protocols. We also conducted measurements to study how traffic gets mixed in the merge network prior to being fed to the switch. We also show that the merge network uses only a fraction of a watt of power, which makes this a very attractive solution for energy efficiency. In this research we have developed solutions that enable linear scaling of energy with load in datacenter networks. The different techniques developed have been analyzed via modeling and simulations as well as prototyping. We believe that these solutions can be easily incorporated into future DCNs with little effort

Investigation of Interconnect and Device Designs for Emerging Post-MOSFET and Beyond Silicon Technologies

Title from PDF of title page viewed May 31, 2017Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 94-108)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2016The integrated circuit industry has been pursuing Moore’s curve down to deep nanoscale dimensions that would lead to the anticipated delivery of 100 billion transistors on a 300 mm² die operating below 1V supply in the next 5-10 years. However, the grand challenge is to reliably and efficiently take the full advantage of the unprecedented computing power offered by the billions of nanoscale transistors on a single chip. To mitigate this challenge, the limitations of both the interconnecting wires and semiconductor devices in integrated circuits have to be addressed. At the interconnect level, the major challenge in current high density integrated circuit is the electromagnetic and electrostatic impacts in the signal carrying lines. Addressing these problems require better analysis of interconnect resistance, inductance, and capacitance. Therefore, this dissertation has proposed a new delay model and analyzed the time-domain output response of complex poles, real poles, and double poles for resistance-inductance capacitance interconnect network based on a second order approximate transfer function. Both analytical models and simulation results show that the real poles model is much faster than the complex poles model, and achieves significantly higher accuracy in order to characterize the overshoot and undershoot of the output responses. On the other hand, the semiconductor industry is anticipating that within a decade silicon devices will be unable to meet the demands at nanoscale due to dimension and material scaling. Recently, molybdenum disulfide (MoS₂) has emerged as a new super material to replace silicon in future semiconductor devices. Besides, conventional field effect transistor technology is also reaching its thermodynamic limit. Breaking this thermal and physical limit requires adoption of new devices based on tunneling mechanism. Keeping the above mentioned trends, this dissertation also proposed a multilayer MoS₂ channel-based tunneling transistor and identifies the fundamental parameters and design specifications that need to be optimized in order to achieve higher ON-currents. A simple analytical model of the proposed device is derived by solving the time-independent Schrodinger equation. It is analytically proven that the proposed device can offer an ON-current of 80 A/m, a subthreshold swing (S) of 9.12 mV/decade, and a / ratio of 10¹².Introduction -- Previous models on interconnect designs -- Proposed delay model for interconnect design -- Investigation of tunneling for field effect transistor -- Study of molybdenum disulfide for FET applications -- Proposed molybdenum disulfide based tunnel transistor -- Conclusion -- Appendix A. Derivation of time delay model -- Appendix B. Derivation of tunneling current model Appendix C. Derivation of subthreshold swing mode