Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Low-Jitter Clock Multiplication: a Comparioson between PLLs and DLLs

This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume more power per cell than their counterparts in the DLL. We can show that this effect is stronger than the notorious jitter accumulation effect that occurs in the voltage-controlled oscillator (VCO) of a PLL. First, an analysis of the stochastic-output jitter of the architectures, due to the most important noise sources, is presented. Then, another important source of jitter in a DLL-based clock multiplier is treated, namely the stochastic mismatch in the delay cells which compose the DLL voltage-controlled delay line (VCDL). An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. A circuit design technique, called impedance level scaling, is then presented which allows the designer to optimize the noise and mismatch behavior of a circuit, independently from other specifications such as speed and linearity. Applying this technique on a delay cell design yields a direct tradeoff between noise induced jitter and power usage, and between stochastic mismatch induced jitter and power usage

A 400 MHz 500-fs-Jitter Open-Loop DLL-Based Multi-Phase Clock Generator Utilizing an Noise-Free All-Digital Locking Detection Circuitry

[[abstract]]An open-loop DLL-based multi-phase clock generator for low jitter applications is designed in 0.13µm CMOS technology. A noise-free all-digital locking detection circuitry (AD-LDC) is designed to detect whether the DLL is locked in time domain. Besides, a current-mismatch free, supplyregulated charge pump is also proposed. As the DLL operating in the open-loop mode, an rms jitter of 500 fs is achieved at the frequency of 400 MHz. The entire circuit occupies 0.01 mm2 and consumes 14 mW. The low jitter multi-phase clock generator can be applied for high-speed ADCs/DACs and wire line transceivers.[[sponsorship]]Hokkaido University[[conferencetype]]國際[[conferencedate]]20120715~20120718[[booktype]]紙本[[iscallforpapers]]Y[[conferencelocation]]Sapporo, Japa

Digital demodulator-correlator

An apparatus for demodulation and correlation of a code modulated 10 MHz signal is presented. The apparatus is comprised of a sample and hold analog-to-digital converter synchronized by a frequency coherent 40 MHz pulse to obtain four evenly spaced samples of each of the signal. Each sample is added or subtracted to or from one of four accumulators to or from the separate sums. The correlation functions are then computed. As a further feature of the invention, multipliers are each multiplied by a squarewave chopper signal having a period that is long relative to the period of the received signal to foreclose contamination of the received signal by leakage from either of the other two terms of the multipliers

Decision feedback loop for tracking a polyphase modulated carrier

A multiple phase modulated carrier tracking loop for use in a frequency shift keying system is described in which carrier tracking efficiency is improved by making use of the decision signals made on the data phase transmitted in each T-second interval. The decision signal is used to produce a pair of decision-feedback quadrature signals for enhancing the loop's performance in developing a loop phase error signal

A Low-Power and High-Speed Frequency Multiplier for DLL-Based Clock Generator

A low-power and high-speed frequency multiplier for a delay-locked loop-based clock generator is proposed to generate a multiplied clock with different range of frequencies. The modified edge combiner consumes low power and achieves a high-speed operation. The proposed frequency multiplier overcomes a deterministic jitter problem by reducing the delay difference between positive- and negative-edge generation paths. The proposed frequency multiplier is implemented in a 0.13-µm CMOS process technology achieved power consumption to a frequency ratio of 2.9 µW/MHz, and has the multiplication ratios of 16, and an output range of 100 MHz–3.3 GHz

A 1.25 Gbit/s serializer for LHC data and trigger optical links

Several LHC detectors require high-speed digital optical links for data transmission in both data readout and trigger systems. Commercial components can be found that meet the bandwidth requirements of most of the LHC detectors subsystems. However, they fail to meet some of the requirements frequently encountered in the LHC-HEP environment, namely: resistance to high radiation doses and operation tolerant to single event upsets. To address these problems, a high-speed transmitter ASIC (1.2Gbit/s), containing a serializer and a clock multiplying PLL was developed. The prototype was implemented in a mainstream 0.25um CMOS technology and was designed using well-established radiation tolerant layout practices to achieve resistance to high radiation doses. This implementation serves as a base for the development of radiation tolerant IC’s that will make feasible the transmission of data using common local area networks protocols in typical LHC radiation hard environments. The ASIC was embedded in a test setup that uses a commercial optical receiver and de-serializer. Error free data transmission at 1.2Gbit/s was achieved proving the prototypes to be fully functional. 1

Radiation Hardened by Design Methodologies for Soft-Error Mitigated Digital Architectures

abstract: Digital architectures for data encryption, processing, clock synthesis, data transfer, etc. are susceptible to radiation induced soft errors due to charge collection in complementary metal oxide semiconductor (CMOS) integrated circuits (ICs). Radiation hardening by design (RHBD) techniques such as double modular redundancy (DMR) and triple modular redundancy (TMR) are used for error detection and correction respectively in such architectures. Multiple node charge collection (MNCC) causes domain crossing errors (DCE) which can render the redundancy ineffectual. This dissertation describes techniques to ensure DCE mitigation with statistical confidence for various designs. Both sequential and combinatorial logic are separated using these custom and computer aided design (CAD) methodologies. Radiation vulnerability and design overhead are studied on VLSI sub-systems including an advanced encryption standard (AES) which is DCE mitigated using module level coarse separation on a 90-nm process with 99.999% DCE mitigation. A radiation hardened microprocessor (HERMES2) is implemented in both 90-nm and 55-nm technologies with an interleaved separation methodology with 99.99% DCE mitigation while achieving 4.9% increased cell density, 28.5 % reduced routing and 5.6% reduced power dissipation over the module fences implementation. A DMR register-file (RF) is implemented in 55 nm process and used in the HERMES2 microprocessor. The RF array custom design and the decoders APR designed are explored with a focus on design cycle time. Quality of results (QOR) is studied from power, performance, area and reliability (PPAR) perspective to ascertain the improvement over other design techniques. A radiation hardened all-digital multiplying pulsed digital delay line (DDL) is designed for double data rate (DDR2/3) applications for data eye centering during high speed off-chip data transfer. The effect of noise, radiation particle strikes and statistical variation on the designed DDL are studied in detail. The design achieves the best in class 22.4 ps peak-to-peak jitter, 100-850 MHz range at 14 pJ/cycle energy consumption. Vulnerability of the non-hardened design is characterized and portions of the redundant DDL are separated in custom and auto-place and route (APR). Thus, a range of designs for mission critical applications are implemented using methodologies proposed in this work and their potential PPAR benefits explored in detail.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201