Characterization and modeling of low-frequency noise in Hf-based high -kappa dielectrics for future cmos applications

The International Technology Roadmap for Semiconductors outlines the need for high-K dielectric based gate-oxide Metal Oxide Semiconductor Field Effect Transistors for sub-45 nm technology nodes. Gate oxides of hafnium seem to be the nearest and best alternative for silicon dioxide, when material, thermal and structural properties are considered. Usage of poly-Si as a gate electrode material degrades the performance of the device and hence gate stacks based on metal gate electrodes are gaining high interest. Though a substantial improvement in the performance has been achieved with these changes, reliability issues are a cause of concern. For analog and mixed-signal applications, low-frequency (I /f~ noise is a major reliability factor. Also in recent years. low frequency noise diagnostics has become a powerful tool for device performance and reliability characterization. This dissertation work demonstrates the necessity of gate stack engineering for achieving a low I/f noise performance. Changes in the material and process parameters of the devices, impact the 1/f noise behavior. The impact of 1/f noise on gate technology and processing parameters xvere identified and investigated. The thickness and the quality of the interfacial oxide, the nitridation effects of the layers, high-K oxide, bulk properties of the high-K layer. percentage of hafnium content in the high-K, post deposition anneal (PDA) treatments, effects of gate electrode material (poly-silicon. fully silicided or metal). Gate electrode processing are investigated in detail. The role of additional interfaces and bulk layers of the gate stack is understood. The dependence of low-frequency noise on high and low temperatures was also investigated. A systematic and a deeper understanding of these parameters on 1/f noise behavior are deduced which also forms the basis for improved physics-based 1/f noise modeling. The model considers the effect of the interfacial layer and also temperature, based on tunneling based thermally activated model. The simulation results of improved drain-current noise model agree well with the experimentally calculated values

Germanium MOS devices integrating high-k dielectric and metal gate

textThis dissertation investigates the fabrication and characteristics of the metaloxide-semiconductor (MOS) devices built on germanium substrates integrating HfO2 high-κ dielectric and TaN metal gate electrode. The metal-gate/high-κ/germanium MOS stack, by taking the advantages of the high carrier mobility from the germanium channel and the sub-nm equivalent-oxide-thickness (EOT) scaling capability from the high-κ dielectric and the metal gate electrode, offers a possible solution for the future advanced complementary MOS (CMOS) applications to further boast the transistors’ driving current for faster operation. Due to the unstable and poor-quality natively grown germanium oxide, surface treatment is very critical in germanium device fabrication in order to remove the native oxide and prevent its growth, as well as suppress the interdiffusion across the interface. Several wet cleaning methods and an in situ cleaning technique by Ar anneal have been investigated. Surface passivation techniques, including NH3-based surface nitridation (SN) by forming a GeOxNy layer and silicon interlayer (SiIL) passivation by growing an ultra-thin (several monolayer) silicon layer between the high-κ dielectric and the substrate, have been studied and proved able to improve device performance significantly. Both p- and n-channel germanium transistors have been successfully fabricated. 1.8X enhancement of peak mobility in p-channel and 2.5X in n-channel over the silicon control devices have been achieved. The interface growth mechanism between the germanium substrate and the dielectric layer has been investigated. Two competing processes occurring at the interface determine the formation of the interfacial layer and affect Ge outdiffusion. Substrate dopants are found playing important roles, which causes the variations in the interfacial layer formation on different types of substrates and so on in the electrical properties. The relatively high diffusivity of dopants and germanium atoms in bulk germanium and the induced structural defects near the surface may severely degrade the device performance. This can well explain the very poor performance of the n-channel devices reported recently by several groups. Performance degradation of the germanium devices after thermal anneal, which is resulting from the interdiffusion and germanium oxide desorption, suggests that thermal stability is a concern in high temperature processes and more stable passivation techniques may be required. Long term reliability study indicates that HfO2 dielectric with SN treatment on germanium is robust against TDDB stress and the long term reliability (TDDB) is not a concern for germanium MOS devices.Electrical and Computer Engineerin

Ultrathin compound semiconductor on insulator layers for high performance nanoscale transistors

Over the past several years, the inherent scaling limitations of electron devices have fueled the exploration of high carrier mobility semiconductors as a Si replacement to further enhance the device performance. In particular, compound semiconductors heterogeneously integrated on Si substrates have been actively studied, combining the high mobility of III-V semiconductors and the well-established, low cost processing of Si technology. This integration, however, presents significant challenges. Conventionally, heteroepitaxial growth of complex multilayers on Si has been explored. Besides complexity, high defect densities and junction leakage currents present limitations in the approach. Motivated by this challenge, here we utilize an epitaxial transfer method for the integration of ultrathin layers of single-crystalline InAs on Si/SiO2 substrates. As a parallel to silicon-on-insulator (SOI) technology14,we use the abbreviation "XOI" to represent our compound semiconductor-on-insulator platform. Through experiments and simulation, the electrical properties of InAs XOI transistors are explored, elucidating the critical role of quantum confinement in the transport properties of ultrathin XOI layers. Importantly, a high quality InAs/dielectric interface is obtained by the use of a novel thermally grown interfacial InAsOx layer (~1 nm thick). The fabricated FETs exhibit an impressive peak transconductance of ~1.6 mS/{\mu}m at VDS=0.5V with ON/OFF current ratio of greater than 10,000 and a subthreshold swing of 107-150 mV/decade for a channel length of ~0.5 {\mu}m

Modeling and Simulation of Subthreshold Characteristics of Short-Channel Fully-Depleted Recessed-Source/Drain SOI MOSFETs

Non-conventional metal-oxide-semiconductor (MOS) devices have attracted researchers‟ attention for future ultra-large-scale-integration (ULSI) applications since the channel length of conventional MOS devices approached the physical limit. Among the non-conventional CMOS devices which are currently being pursued for the future ULSI, the fully-depleted (FD) SOI MOSFET is a serious contender as the SOI MOSFETs possess some unique features such as enhanced short-channel effects immunity, low substrate leakage current, and compatibility with the planar CMOS technology. However, due to the ultra-thin source and drain regions, FD SOI MOSFETs possess large series resistance which leads to the poor current drive capability of the device despite having excellent short-channel characteristics. To overcome this large series resistance problem, the source/drain area may be increased by extending S/D either upward or downward. Hence, elevated-source/drain (E-S/D) and recessed-source/drain (Re-S/D) are the two structures which can be used to minimize the series resistance problem. Due to the undesirable issues such as parasitic capacitance, current crowding effects, etc. with E-S/D structure, the Re-S/D structure is a better choice. The FD Re-S/D SOI MOSFET may be an attractive option for sub-45nm regime because of its low parasitic capacitances, reduced series resistance, high drive current, very high switching speed and compatibility with the planar CMOS technology. The present dissertation is to deal with the theoretical modeling and computer-based simulation of the FD SOI MOSFETs in general, and recessed source/drain (Re-S/D) ultra-thin-body (UTB) SOI MOSFETs in particular. The current drive capability of Re-S/D UTB SOI MOSFETs can be further improved by adopting the dual-metal-gate (DMG) structure in place of the conventional single-metal-gate-structure. However, it will be interesting to see how the presence of two metals as gate contact changes the subthreshold characteristics of the device. Hence, the effects of adopting DMG structure on the threshold voltage, subthreshold swing and leakage current of Re-S/D UTB SOI MOSFETs have been studied in this dissertation. Further, high-k dielectric materials are used in ultra-scaled MOS devices in order to cut down the quantum mechanical tunneling of carriers. However, a physically thick gate dielectric causes fringing field induced performance degradation. Therefore, the impact of high-k dielectric materials on subthreshold characteristics of Re-S/D SOI MOSFETs needs to be investigated. In this dissertation, various subthreshold characteristics of the device with high-k gate dielectric and metal gate electrode have been investigated in detail. Moreover, considering the variability problem of threshold voltage in ultra-scaled devices, the presence of a back-gate bias voltage may be useful for ultimate tuning of the threshold voltage and other characteristics. Hence, the impact of back-gate bias on the important subthreshold characteristics such as threshold voltage, subthreshold swing and leakage currents of Re-S/D UTB SOI MOSFETs has been thoroughly analyzed in this dissertation. The validity of the analytical models are verified by comparing model results with the numerical simulation results obtained from ATLAS™, a device simulator from SILVACO Inc

Electrodeposited Ni/Ge and germanide schottky barriers for nanoelectronics applications

In recent years metal/semiconductor Schottky barriers have found numerous applications in nanoelectronics. The work presented in this thesis focuses on the improvement of a few of the relevant devices using electrodeposition of metal on Ge for Schottky barrier fabrication. This low energy metallisation technique offers numerous advantages over the physical vapour deposition techniques. Electrical characteristics of the grown diodes show a high quality rectifying behaviour with extremely low leakage currents even on highly doped Ge. A non-Arrhenius behaviour of the temperature dependence is observed for the grown Ni/Ge diodes on lowly doped Ge that is explained by a spatial variation of the barrier heights. The inhomogeneity of the barrier hights is explained in line with an intrinsic surface states model for Ge. The understanding of the intrinsic surface states will help to create ohmic contacts for doped n-MOSFETs. NiGe were formed single phase by annealing. Results reveal that by using these high-quality germanide Schottky barriers as the source/drain, the subthreshold leakage currents of a Schottky barrier MOSFET could be minimised, in particular, due to the very low drain/body junction leakage current exhibited by the electrodeposited diodes. The Ni/Ge diodes on highly doped Ge show negative differential conductance at low temperature. This effect is attributed to the intervalley electron transfer in Ge conduction band to a low mobility valley. The results show experimentally that Schottky junctions could be used for hot electron injection in transferred-electron devices. A vertical Co/Ni/Si structure has been fabricated for spin injection and detection in Si. It is shown that the system functions electrically well although no magnetoresistance indicative of spin injection was observed

Improved electrical properties of Ge p-MOSFET with HfO 2 gate dielectric by using TaO xN y interlayer

The electrical characteristics of germanium p-metal-oxide-semiconductor (p-MOS) capacitor and p-MOS field-effect transistor (FET) with a stack gate dielectric of HfO 2TaO xN y are investigated. Experimental results show that MOS devices exhibit much lower gate leakage current than MOS devices with only HfO 2 as gate dielectric, good interface properties, good transistor characteristics, and about 1.7-fold hole-mobility enhancement as compared with conventional Si p-MOSFETs. These demonstrate that forming an ultrathin passivation layer of TaO xN y on germanium surface prior to deposition of high- k dielectrics can effectively suppress the growth of unstable GeO x, thus reducing interface states and increasing carrier mobility in the inversion channel of Ge-based transistors. © 2008 IEEE.published_or_final_versio

III-V and 2D Devices: from MOSFETs to Steep-Slope Transistors

With silicon CMOS technology approaching the scaling limit, alternating channel materials and novel device structures have been extensively studied and attracted a lot of attention in solid-state device research. In this dissertation, solid-state electron devices for post-Si CMOS applications are explored including both new materials such as III-V and 2D materials and new device structures such as tunneling field-effect transistors and negative capacitance field-effect transistors. Multiple critical challenges in applying such new materials and new device structures are addressed and the key achievements in this dissertation are summarized as follows: 1) Development of fabrication process technology for ultra-scaled planar and 3D InGaAs MOSFETs. 2) Interface passivation by forming gas anneal on InGaAs gate-all-around MOSFETs. 3) Characterization methods for ultra-scaled MOSFETs, including a correction to subthreshold method and low frequency noise characterization in short channel devices. 4) Development of short channel InGaAs planar and 3D gate-allaround tunneling field-effect transistors. 5) Negative capacitance field-effect transistors with hysteresis-free and bi-directional sub-thermionic subthreshold slope and the integration with various channel materials such as InGaAs and MoS2

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book