An efficient unused integrated circuits detection algorithm for parallel scan architecture

In recent days, many integrated circuits (ICs) are operated parallelly to increase switching operations in on-chip static random access memory (SRAM) array, due to more complex tasks and parallel operations being executed in many digital systems. Hence, it is important to efficiently identify the long-duration unused ICs in the on-chip SRAM memory array layout and to effectively distribute the task to unused ICs in SRAM memory array. In the present globalization, semiconductor supply chain detection of unused SRAM in large memory arrays is a very difficult task. This also results in reduced lifetime and more power dissipation. To overcome the above-mentioned drawbacks, an efficient unused integrated circuits detection algorithm (ICDA) for parallel scan architecture is proposed to differentiate the ‘0’ and ‘1’ in a larger SRAM memory array. The proposed architecture avoids the unbalancing of ‘0’ and ‘1’ concentrations in the on-chip SRAM memory array and also optimizes the area required for the memory array. As per simulation results, the proposed method is more efficient in terms of reliability, the detection rate in both used and unused ICs and reduction of power dissipation in comparison to conventional methods such as backscattering side-channel analysis (BSCA) and network attached storage (NAS) algorithm

Techniques for Improving Security and Trustworthiness of Integrated Circuits

The integrated circuit (IC) development process is becoming increasingly vulnerable to malicious activities because untrusted parties could be involved in this IC development flow. There are four typical problems that impact the security and trustworthiness of ICs used in military, financial, transportation, or other critical systems: (i) Malicious inclusions and alterations, known as hardware Trojans, can be inserted into a design by modifying the design during GDSII development and fabrication. Hardware Trojans in ICs may cause malfunctions, lower the reliability of ICs, leak confidential information to adversaries or even destroy the system under specifically designed conditions. (ii) The number of circuit-related counterfeiting incidents reported by component manufacturers has increased significantly over the past few years with recycled ICs contributing the largest percentage of the total reported counterfeiting incidents. Since these recycled ICs have been used in the field before, the performance and reliability of such ICs has been degraded by aging effects and harsh recycling process. (iii) Reverse engineering (RE) is process of extracting a circuit’s gate-level netlist, and/or inferring its functionality. The RE causes threats to the design because attackers can steal and pirate a design (IP piracy), identify the device technology, or facilitate other hardware attacks. (iv) Traditional tools for uniquely identifying devices are vulnerable to non-invasive or invasive physical attacks. Securing the ID/key is of utmost importance since leakage of even a single device ID/key could be exploited by an adversary to hack other devices or produce pirated devices. In this work, we have developed a series of design and test methodologies to deal with these four challenging issues and thus enhance the security, trustworthiness and reliability of ICs. The techniques proposed in this thesis include: a path delay fingerprinting technique for detection of hardware Trojans, recycled ICs, and other types counterfeit ICs including remarked, overproduced, and cloned ICs with their unique identifiers; a Built-In Self-Authentication (BISA) technique to prevent hardware Trojan insertions by untrusted fabrication facilities; an efficient and secure split manufacturing via Obfuscated Built-In Self-Authentication (OBISA) technique to prevent reverse engineering by untrusted fabrication facilities; and a novel bit selection approach for obtaining the most reliable bits for SRAM-based physical unclonable function (PUF) across environmental conditions and silicon aging effects

A survey on security analysis of machine learning-oriented hardware and software intellectual property

Intellectual Property (IP) includes ideas, innovations, methodologies, works of authorship (viz., literary and artistic works), emblems, brands, images, etc. This property is intangible since it is pertinent to the human intellect. Therefore, IP entities are indisputably vulnerable to infringements and modifications without the owner’s consent. IP protection regulations have been deployed and are still in practice, including patents, copyrights, contracts, trademarks, trade secrets, etc., to address these challenges. Unfortunately, these protections are insufficient to keep IP entities from being changed or stolen without permission. As for this, some IPs require hardware IP protection mechanisms, and others require software IP protection techniques. To secure these IPs, researchers have explored the domain of Intellectual Property Protection (IPP) using different approaches. In this paper, we discuss the existing IP rights and concurrent breakthroughs in the field of IPP research; provide discussions on hardware IP and software IP attacks and defense techniques; summarize different applications of IP protection; and lastly, identify the challenges and future research prospects in hardware and software IP security

Ingress of threshold voltage-triggered hardware trojan in the modern FPGA fabric–detection methodology and mitigation

The ageing phenomenon of negative bias temperature instability (NBTI) continues to challenge the dynamic thermal management of modern FPGAs. Increased transistor density leads to thermal accumulation and propagates higher and non-uniform temperature variations across the FPGA. This aggravates the impact of NBTI on key PMOS transistor parameters such as threshold voltage and drain current. Where it ages the transistors, with a successive reduction in FPGA lifetime and reliability, it also challenges its security. The ingress of threshold voltage-triggered hardware Trojan, a stealthy and malicious electronic circuit, in the modern FPGA, is one such potential threat that could exploit NBTI and severely affect its performance. The development of an effective and efficient countermeasure against it is, therefore, highly critical. Accordingly, we present a comprehensive FPGA security scheme, comprising novel elements of hardware Trojan infection, detection, and mitigation, to protect FPGA applications against the hardware Trojan. Built around the threat model of a naval warship’s integrated self-protection system (ISPS), we propose a threshold voltage-triggered hardware Trojan that operates in a threshold voltage region of 0.45V to 0.998V, consuming ultra-low power (10.5nW), and remaining stealthy with an area overhead as low as 1.5% for a 28 nm technology node. The hardware Trojan detection sub-scheme provides a unique lightweight threshold voltage-aware sensor with a detection sensitivity of 0.251mV/nA. With fixed and dynamic ring oscillator-based sensor segments, the precise measurement of frequency and delay variations in response to shifts in the threshold voltage of a PMOS transistor is also proposed. Finally, the FPGA security scheme is reinforced with an online transistor dynamic scaling (OTDS) to mitigate the impact of hardware Trojan through run-time tolerant circuitry capable of identifying critical gates with worst-case drain current degradation

Smartphone-based molecular sensing for advanced characterization of asphalt concrete materials

Pavement systems deteriorate with time due to the aging of materials, excessive use, overloading, climatic conditions, inadequate maintenance, and deficiencies in inspection methods. Proper evaluation of pavement conditions provides important decision-support to implement preventative rehabilitation. This study presents an innovative smartphone-based monitoring method for advanced characterization of asphalt concrete materials. The proposed method is based on deploying a pocket-sized near-infrared (NIR) molecular sensor that is fully integrated with smartphones. The NIR spectrometer illuminates a sample with a broad-spectrum of near-infrared light, which can be absorbed, transmitted, reflected, or scattered by the sample. The light intensity is measured as a function of wavelength before and after interacting with the sample. Thereafter, the diffuse reflectance, a combination of absorbance and scattering, caused by the sample is calculated. This portable smartphone-based NIR method is used to detect asphalt binders with various performance grading (PG) and aging levels. To this end, a number of binder samples are tested in a wavelength range of 740 to 1070 nm. The results indicate that asphalt binders with different grades and aging levels yield significantly different spectrums. These distinctive spectrums can be attributed to the variations of binder components such as saturate, asphaltenic, resin, and aromatic. Furthermore, the molecular sensor is successfully deployed to detect and classify asphalt mixtures fabricated with a various binder and recycled material types such as styrene-butadiene-styrene (SBS), ground tire rubber (SBS), engineered crumbed rubber (ECR), reclaimed asphalt pavement (RAP), and recycled asphalt shingles (RAS). The proposed monitoring technology is not only a viable tool for asphalt material characterization but also a cost-effective platform capable of transforming the current physical and chemical methods for civil engineering material characterization.Includes bibliographical reference

ToSHI - Towards Secure Heterogeneous Integration: Security Risks, Threat Assessment, and Assurance

The semiconductor industry is entering a new age in which device scaling and cost reduction will no longer follow the decades-long pattern. Packing more transistors on a monolithic IC at each node becomes more difficult and expensive. Companies in the semiconductor industry are increasingly seeking technological solutions to close the gap and enhance cost-performance while providing more functionality through integration. Putting all of the operations on a single chip (known as a system on a chip, or SoC) presents several issues, including increased prices and greater design complexity. Heterogeneous integration (HI), which uses advanced packaging technology to merge components that might be designed and manufactured independently using the best process technology, is an attractive alternative. However, although the industry is motivated to move towards HI, many design and security challenges must be addressed. This paper presents a three-tier security approach for secure heterogeneous integration by investigating supply chain security risks, threats, and vulnerabilities at the chiplet, interposer, and system-in-package levels. Furthermore, various possible trust validation methods and attack mitigation were proposed for every level of heterogeneous integration. Finally, we shared our vision as a roadmap toward developing security solutions for a secure heterogeneous integration

Printed and drawn flexible electronics based on cellulose nanocomposites

Sustainability, flexibility, and low-power consumption are key features to meet the growing re- quirements of simplicity and multifunctionality of low-cost, disposable/recyclable smart electronic -of- -based composites hold po- tential to fulfill such demands when explored as substrate and/or electrolyte-gate, or as active channel layer on printed transistors and integrated circuits based on ionic responses (iontronics). In this work, a new generation of reusable, healable and recyclable regenerated cellulose hydro- gels with high ionic conductivity and conformability, capable of being provided in the form of stick- ers, are demonstrated. These hydrogels are obtained from a simple, fast, low-cost, and environ- mental-friendly aqueous alkali salt/urea dissolution method of native cellulose, combined with eration and simultaneous ion incorporation with acetic acid. Their electrochemical properties can be also merged with the mechanical robustness, thermal resistance, transparency, and smooth- - strate. Beyond gate dielectrics, a water-based screen-printable ink, composed of CMC binder and com- mercial zinc oxide (ZnO) semiconducting nanoparticles, was formulated. The ink enables the printing of relatively smooth and densely packed films on office paper with semiconducting func- tionality at room temperature. The rather use of porous ZnO nanoplates is beneficial to form per- colative pathways at lower contents of functional material, at the cost of rougher surfaces. The engineered cellulose composites are successfully integrated into flexible, recyclable, low- voltage (<3.5 V), printed electrolyte-gated office paper or on the ionically modified nanopaper. Ubiquitous calligraphy accessories are used -the- out on the target substrate, where are already printed the devices. Such concept paves the way for a worldwide boom of creativity, where we can freely create personal electronic kits, while having fun at it and without generating waste.Sustentabilidade, flexibilidade e baixo consumo energético são características chave para atender aos crescentes requisitos de simplicidade e multifuncionalidade de sistemas eletrónicos inteligentes de baixo custo, das- Compósitos à base de celulose têm potencial para atender a tais necessidades quando explora- dos como substrato e/ou porta-de-eletrólito ou como camada de canal ativo em transístores impressos e circuitos integrados baseados em respostas iónicas (iontronics). Neste trabalho, é demonstrada uma nova geração de hidrogéis reutilizáveis, reparáveis e recicláveis baseados em celulose regenerada, que apresentam alta condução iónica e conformabilidade, podendo ser fornecidos na forma de adesivos. Estes hidrogéis são obtidos a partir de um método simples, rápido, barato e amigo do ambiente que permite a dissolução de celulose nativa em soluções aquosas com mistura de sal alcalino e ureia, combinado com carboximetil celulose (CMC) para melhorar a sua robustez, seguido da regeneração e simultâneo enriquecimento iónico com ácido acético. As suas propriedades eletroquímicas podem ser combinadas com a inbase de celulose micro/nanofibrilada para obter um substrato eletrolítico semelhante a papel. Para além de portas-dielétricas, foi formulada uma tinta aquosa compatível com serigrafia, composta por CMC como espessante e nanopartículas semicondutoras de ZnO. A tinta permite a impressão de filmes pouco rugosos e densamente percolados sobre papel de escritório, e com funcionalidade semicondutora à temperatura ambiente. O uso alternativo de nanoplacas porosas de ZnO é benéfico para criar caminhos percolativos com menores teores de material funcional, apesar de se obter filmes rugosos. Os compósitos à base celulose foram integrados com sucesso em transístores e portas lógicas porta-eletrolítica, os quais foram impressos em papel de escritório ou no "nanopapel" iconicamente modificado. Acessórios de caligrafia permitem a fácil e rápida padronização de pistas condutoras/resistivas, desenhando-as no substrato alvo, onde estão impressos os dispositivos. Este conceito despoleta um mundo criativo, onde é possível criar livremente kits eletrónicos customizados de forma divertida e sem gerar resíduos