65 research outputs found
Lempel-Ziv Data Compression on Parallel and Distributed Systems
We present a survey of results concerning Lempel-Ziv data compression on parallel and distributed systems, starting from the theoretical approach to parallel time complexity to conclude with the practical goal of designing distributed algorithms with low communication cost. An extension by Storer to image compression is also discussed
Gbit/second lossless data compression hardware
This thesis investigates how to improve the performance of lossless data compression hardware
as a tool to reduce the cost per bit stored in a computer system or transmitted over a
communication network.
Lossless data compression allows the exact reconstruction of the original data after
decompression. Its deployment in some high-bandwidth applications has been hampered due to
performance limitations in the compressing hardware that needs to match the performance of the
original system to avoid becoming a bottleneck. Advancing the area of lossless data compression
hardware, hence, offers a valid motivation with the potential of doubling the performance of the
system that incorporates it with minimum investment.
This work starts by presenting an analysis of current compression methods with the objective of
identifying the factors that limit performance and also the factors that increase it. [Continues.
A novel approach for the hardware implementation of a PPMC statistical data compressor
This thesis aims to understand how to design high-performance compression
algorithms suitable for hardware implementation and to provide hardware support for
an efficient compression algorithm.
Lossless data compression techniques have been developed to exploit the available
bandwidth of applications in data communications and computer systems by reducing
the amount of data they transmit or store. As the amount of data to handle is ever
increasing, traditional methods for compressing data become· insufficient. To
overcome this problem, more powerful methods have been developed. Among those
are the so-called statistical data compression methods that compress data based on
their statistics. However, their high complexity and space requirements have prevented
their hardware implementation and the full exploitation of their potential benefits.
This thesis looks into the feasibility of the hardware implementation of one of these
statistical data compression methods by exploring the potential for reorganising and
restructuring the method for hardware implementation and investigating ways of
achieving efficient and effective designs to achieve an efficient and cost-effective
algorithm. [Continues.
Accuracy and performance of the lattice Boltzmann method with 64-bit, 32-bit, and customized 16-bit number formats
Fluid dynamics simulations with the lattice Boltzmann method (LBM) are very
memory-intensive. Alongside reduction in memory footprint, significant
performance benefits can be achieved by using FP32 (single) precision compared
to FP64 (double) precision, especially on GPUs. Here, we evaluate the
possibility to use even FP16 and Posit16 (half) precision for storing fluid
populations, while still carrying arithmetic operations in FP32. For this, we
first show that the commonly occurring number range in the LBM is a lot smaller
than the FP16 number range. Based on this observation, we develop novel 16-bit
formats - based on a modified IEEE-754 and on a modified Posit standard - that
are specifically tailored to the needs of the LBM. We then carry out an
in-depth characterization of LBM accuracy for six different test systems with
increasing complexity: Poiseuille flow, Taylor-Green vortices, Karman vortex
streets, lid-driven cavity, a microcapsule in shear flow (utilizing the
immersed-boundary method) and finally the impact of a raindrop (based on a
Volume-of-Fluid approach). We find that the difference in accuracy between FP64
and FP32 is negligible in almost all cases, and that for a large number of
cases even 16-bit is sufficient. Finally, we provide a detailed performance
analysis of all precision levels on a large number of hardware
microarchitectures and show that significant speedup is achieved with mixed
FP32/16-bit.Comment: 30 pages, 20 figures, 4 tables, 2 code listing
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