Ultra-wideband and highly linear 43-97 GHz receiver front-end

This research presents a wideband mmWave receiver front-end that covers the frequency range from 43 to 97 GHz, supporting the operation in the major parts of the V-, E- and W-bands. The front-end incorporates a passive mixer-first topology to achieve high linearity and wideband performance along with an optimum operational instantaneous bandwidth. In addition, it implements the multi-gate gm3 cancellation technique at the IF amplifiers to preserve the linearity and provide gain at the IF section. Image rejection capabilities using a current mode transformer based IF 90o coupler is implemented on chip and demonstrated with measurements. The front-end is fabricated on the Globelfoundries 22nm FD-SOI CMOS process and demonstrates an ultra-wideband performance across the frequency range 43-97 GHz (2.25:1 bandwidth) with image rejection of up to 32 dB, IIP3 of 1.6-5.2 dBm and gain of 15 dB. Furthermore, the measurement results show that the front-end supports high speed modulated signals of up to 6 Gbps 64QAM modulation data.M.S

Millimeter-Wave Wideband Low-Noise Amplifiers in 22FFL Technology

The deployment of advanced technology standards for 5G and beyond in cellular networks has resulted in interest in integrated circuits (ICs) operating at frequencies above 10GHz. This has sparked research on wideband circuits in commercial low-cost silicon technologies, operating at high RF and mm-wave frequencies. Given the wide range of operating frequencies (28GHz, 30GHz and 47GHz), such circuits must satisfy performance parameters across wide operating range. This thesis focuses on the implementation of wideband low-noise amplifiers (LNA) and addresses design challenges associated with mm-wave wideband impedance matching networks in state-of-the-art CMOS technologies

HIGH LINEARITY UNIVERSAL LNA DESIGNS FOR NEXT GENERATION WIRELESS APPLICATIONS

Design of the next generation (4G) systems is one of the most active and important area of research and development in wireless communications. The 2G and 3G technologies will still co-exist with the 4G for a certain period of time. Other applications such as wireless LAN (Local Area Network) and RFID are also widely used. As a result, there emerges a trend towards integrating multiple wireless functionalities into a single mobile device. Low noise amplifier (LNA), the most critical component of the receiver front-end, determines the sensitivity and noise figure of the receiver and is indispensable for the complete system. To satisfy the need for higher performance and diversity of wireless communication systems, three LNAs with different structures and techniques are proposed in the thesis based on the 4G applications. The first LNA is designed and optimized specifically for LTE applications, which could be easily added to the existing system to support different standards. In this cascode LNA, the nonlinearity coming from the common source (CS) and common gate (CG) stages are analyzed in detail, and a novel linear structure is proposed to enhance the linearity in a relatively wide bandwidth. The LNA has a bandwidth of 900MHz with the linearity of greater than 7.5dBm at the central frequency of 1.2GHz. Testing results show that the proposed structure effectively increases and maintains linearity of the LNA in a wide bandwidth. However, a broadband LNA that covers multiple frequency ranges appears more attractive due to system simplicity and low cost. The second design, a wideband LNA, is proposed to cover multiple wireless standards, such as LTE, RFID, GSM, and CDMA. A novel input-matching network is proposed to relax the tradeoff among noise figure and bandwidth. A high gain (>10dB) in a wide frequency range (1-3GHz) and a minimum NF of 2.5dB are achieved. The LNA consumes only 7mW on a 1.2V supply. The first and second LNAs are designed mainly for the LTE standard because it is the most widely used standard in the 4G communication systems. However, WiMAX, another 4G standard, is also being widely used in many applications. The third design targets on covering both the LTE and the WiMAX. An improved noise cancelling technique with gain enhancing structure is proposed in this design and the bandwidth is enlarged to 8GHz. In this frequency range, a maximum power gain of 14.5dB and a NF of 2.6-4.3dB are achieved. The core area of this LNA is 0.46x0.67mm2 and it consumes 17mW from a 1.2V supply. The three designs in the thesis work are proposed for the multi-standard applications based on the realization of the 4G technologies. The performance tradeoff among noise, linearity, and broadband impedance matching are explored and three new techniques are proposed for the tradeoff relaxation. The measurement results indicate the techniques effectively extend the bandwidth and suppress the increase of the NF and nonlinearity at high frequencies. The three proposed structures can be easily applied to the wideband and multi-standard LNA design

ANALYSIS AND DESIGN OF SILICON-BASED MILLIMETER-WAVE AMPLIFIERS

Ph.DDOCTOR OF PHILOSOPH

Wireless wire - ultra-low-power and high-data-rate wireless communication systems

With the rapid development of communication technologies, wireless personal-area communication systems gain momentum and become increasingly important. When the market gets gradually saturated and the technology becomes much more mature, new demands on higher throughput push the wireless communication further into the high-frequency and high-data-rate direction. For example, in the IEEE 802.15.3c standard, a 60-GHz physical layer is specified, which occupies the unlicensed 57 to 64 GHz band and supports gigabit links for applications such as wireless downloading and data streaming. Along with the progress, however, both wireless protocols and physical systems and devices start to become very complex. Due to the limited cut-off frequency of the technology and high parasitic and noise levels at high frequency bands, the power consumption of these systems, especially of the RF front-ends, increases significantly. The reason behind this is that RF performance does not scale with technology at the same rate as digital baseband circuits. Based on the challenges encountered, the wireless-wire system is proposed for the millimeter wave high-data-rate communication. In this system, beamsteering directional communication front-ends are used, which confine the RF power within a narrow beam and increase the level of the equivalent isotropic radiation power by a factor equal to the number of antenna elements. Since extra gain is obtained from the antenna beamsteering, less front-end gain is required, which will reduce the power consumption accordingly. Besides, the narrow beam also reduces the interference level to other nodes. In order to minimize the system average power consumption, an ultra-low power asynchronous duty-cycled wake-up receiver is added to listen to the channel and control the communication modes. The main receiver is switched on by the wake-up receiver only when the communication is identified while in other cases it will always be in sleep mode with virtually no power consumed. Before transmitting the payload, the event-triggered transmitter will send a wake-up beacon to the wake-up receiver. As long as the wake-up beacon is longer than one cycle of the wake-up receiver, it can be captured and identified. Furthermore, by adopting a frequency-sweeping injection locking oscillator, the wake-up receiver is able to achieve good sensitivity, low latency and wide bandwidth simultaneously. In this way, high-data-rate communication can be achieved with ultra-low average power consumption. System power optimization is achieved by optimizing the antenna number, data rate, modulation scheme, transceiver architecture, and transceiver circuitries with regards to particular application scenarios. Cross-layer power optimization is performed as well. In order to verify the most critical elements of this new approach, a W-band injection-locked oscillator and the wake-up receiver have been designed and implemented in standard TSMC 65-nm CMOS technology. It can be seen from the measurement results that the wake-up receiver is able to achieve about -60 dBm sensitivity, 10 mW peak power consumption and 8.5 µs worst-case latency simultaneously. When applying a duty-cycling scheme, the average power of the wake-up receiver becomes lower than 10 µW if the event frequency is 1000 times/day, which matches battery-based or energy harvesting-based wireless applications. A 4-path phased-array main receiver is simulated working with 1 Gbps data rate and on-off-keying modulation. The average power consumption is 10 µW with 10 Gb communication data per day

Analogue circuits for low power communication

Low power electronic circuits are required to extend the operational time of battery operated devices. They are also necessary to reduce the power consumption of equipment in general, especially as the world tries to cut energy usage. The first section of this thesis explores fundamental and implementation limits for low power circuits. The energy requirements of amplification are presented and a lower bound on the energy required to transmit information over a point to point link is proposed. It is evident from the low power limits survey that when a transistor is biased, significant thermodynamic energy is required to reduce the resistance of the channel. A transmitter is presented that turns on a transistor for 0.1 % of transmitted time. This transmitter approximates a Gaussian pulse by allowing the impulse response of two 2nd order transmitting elements to sum in free space. The transmitter is of low complexity and the receiver architecture ensures that no on-line tuning is required. Measured results indicate that by using coherent detection a 1 Mbps, 50 mm distance link with a bit error rate of 10−3 can be achieved. The bandwidth of the transmitted pulse is 30-37.5 MHz and 30 dB of out of band attenuation is provided. An analogue Gabor transform is described which splits a signal into parallel paths of a lower bandwidth. This enables post processing at lower clock rates, which can reduce energy dissipation. An implementation of the transform using sub-threshold CMOS continuous time filters is presented. A novel method for designing low power gmC filters using simple models of identical transconductors is used to specify transistor sizes. Measured results show that the transform consumes 7 μW for an input signal bandwidth of 4 kHz